Hi Sren,
The port is a testbench tool, so a layout view is not required. In the cadence tool it is analogLib/port.

Your extracted layout view of your circuit should be instantiated in a testbench and stimulated by the analogLib port (as well as things like vdc, idc etc.).

In the Cadence flow you can use the heirarchy editor (config view) to control the netlister so you can simulate the circuit schematic or extracted layout in the same testbench.

hope this helps

aw