Hi everybody,
From an analog designer's point of view, I fully agree with the points of view expressed above. However, from a practical point of view, I'm not convinced MC simulation is a feasible alternative in all cases. Beyond the foundry support issue (which is a real problem), statistical simulation time may become too important if you want the statistics to be relevant. With corner simulations, you considerably reduce the amount of simulations you have to run and unsurprisingly you reduce the amount of information you get (nothing's for free...).
Yawei, your example doesn't hold to show the irrelevance of corner simulations, because the later corner sim revealed the issue. I must say that it is the designer's fault if he reduces the number of corners and omits some critical corners. I don't believe you would have seen the problem in MC simulations if you had omitted the 3.3V supply case.
Finally, as process engineers implement more and more compensation methods to tune the process for parameter variations, I wonder in how far the Gaussian assumption behind most MC models will hold for the sub 90nm nodes... Any info on this is welcome.
Interestingly some EDA providers start to deliver tools for yield optimization and design centering. I wonder how these will work with the current corner models we get
As design kits, as well as processes, are made for the mass (i.e. the digital designers), I don't think we can expect improved foundry support soon. We will probably have to stick with our "darned" corner simulations or trust our custom-made MC models.
Paul