Hi all,

I followed some advice I recently got on this forum and changed my LNA biasing to improve the Linearity, but to do this I need to use the input RF transistors of my LNA as the other side of a current mirror. In other words picture on the left leg a cascode current mirror biased with IPTAT and on the right leg is my cascode LNA. The gates of the two legs are connected by a large resistor and the current mirror noise is grounded by a large capacitor.

So anyway my problem is that while i seem to be getting good current-temperature variation, the matching is off. My LNA RF transistors are 5 times the size of the current mirror transistors but the current is more than 10 times the value. One thing is that i'm using minimum device length since it is at RF, so i expect poor matching...but not that poor. This primitive diagram might help (see below)...its obviously not and exact design but basically while W/L of B is 10 times W/L of A, the current through A is more than 20 times that of B. All transistors are minimum length (0.18u). One other thing is probably very important is that the transistors are operating very close to the threshold voltage. You may even say they are in the subthreshold region...

Tips would be great since it took me ages to draw that diagram....thanks,

Aaron


Ibias     gnd             vdd
  l          l                 >
  l         =                 >
  l ___    l                 >  
  l__   l   l              __l------ll----RFout
A  __ll------vvvv---ll__  B
  l                             l
  l____                      l
  l__   l                  __l  
A  __ll------vvvv---ll__  B
  l         l          l        l
  l        =          l        l
  l         l         rfin    gnd
gnd     gnd

Hi ACWWong,

nice to hear from you...I double checked and there's definately twice as much current in the LNA so its not because I accidently read both differential sides. Theres also no degeneration resistor. You understood my question correctly so I guess there's some other problem...

Also, I didn't want to clamp the gate of my cascode device (side A)  to VDD since this will cause the DC current to vary with VDD. My design is supposed to be relatively immune to supply variation.

thanks for all the help,

Aaron

aaron_do wrote on May 3^rd, 2006, 6:23pm:


with regards to the bias, I meant tieing cascode B gate to vdd, and using top device A as a diode. doing this will not degrade current variation. What it will do will make the the casccode B device act more like a common gate and you no longer need the top R & C.

Ibias             vdd       vdd
  l                    l         >
  l                    |       >
  l ___              l        >  
  l__   l             l    __l------ll----RFout  
A  __ll--            ---ll__  B
  l                             l
  l____                      l
  l__   l                  __l  
A  __ll------vvvv---ll__  B
  l         l          l        l
  l        =          l        l
  l         l         rfin    gnd
gnd     gnd

Thanks Alan,

I'll check up about the netlist, but i'm a little sceptical that that's the problem since I've tried using both RF transistor models and standard analog models in the left leg of the current mirror.

Also the mismatch only appears for the smaller device widths (total width and different width per finger seem to give same results) when I use a larger device on the left leg I get a correct match...of course the tradeoff is higher power consumption.

I've heard that there is some dependence of VT on device width so this could be the reason especially since I am using weak inversion where a small change in VT can result in a large change in I. If you happen to know about this dependence could you refer me to any papers?

thanks,
Aaron

BTW I actually misplaced the capacitor on my cascode device since it should connect directly to B sides gate to make it more common gate...just thought i'd clarify