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plotting verilog-a internals? (Read 6542 times)

danmc Community Member Offline Posts: 35 Boston	plotting verilog-a internals? May 06^th, 2006, 9:10pm anyone know how (if possible) to plot an internal signal (electricaltype in my case) from a verilog-a module? The signal does not go to a pin. I'm using cadence. I took a look in the results browser in analog artist but didn't see any of the internal nets inside the veriloga model. Thanks -Dan
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sheldon

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Posts: 751

Re: plotting verilog-a internals?
Reply #1 - May 6^th, 2006, 9:26pm

Dan,

� Doing this from memory, in the Outputs --> Save All window, select
save ahdl variables radio button. This should allow you to save and
plot the variables. However, you may need to access them from the
Results Browser.

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � Best Regards,

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �Sheldon

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danmc Community Member Offline Posts: 35 Boston	Re: plotting verilog-a internals? Reply #2 - May 7^th, 2006, 8:28pm This almost works. I now see anything of type 'real' in the results browser, but still no 'electrical' ones. So, for now I just stuck in: electrical foo; real vfoo; analog begin vfoo = V(foo); // other stuff end to make my signal show up as a real. Thanks -Dan
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sheldon Community Fellow Offline Posts: 751	Re: plotting verilog-a internals? Reply #3 - May 8^th, 2006, 6:18pm Dan, Oops in that case, try setting the option "select signals to output (save)" to all in the Outputs --> Save All... window. Eletrical nodes internal to a behavioral model are not public and are not saved by default (as I remember). Best Regards, Sheldon
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ACWWong Community Fellow Offline Posts: 539 Oxford, UK	Re: plotting verilog-a internals? Reply #4 - May 9^th, 2006, 12:36am Yes, default is "allpub", so changing it to "all" should give all internal nodes....
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