Hi Peter,

I think it is undesirable to place current mirrors in weak inversion. Let me list some reasons:

1. Matching is poor. Current mismatch in current mirrors will get worse with smaller (VGS-VT). In fact,
it should normally be quite poor in weak inversion regime.

2. Noise from the current mirrors will shoot up. By placing transistors in weak inversion region, you are maximizing
Gm/I for these devices. As a result, the noise contribution is significant, especially if the current mirror happens to be
used in an opamp as an active load. Of course, then you would also have to worry about its speed.

3. The mirror will be very slow. It is worth remembering that even if you are simply using the mirror to feed in a DC current,
you do expect the mirror output to stay undisturbed due to changing signals elsewhere or in the circuit which the mirror is feeding.
Otherwise, performance of the whole circuit is affected. Fast circuits need fast-responding bias as well.

4. Finally, your simulations are only as good as your models. While some foundries specializing in analog processes may characterize
the operation in weak inversion well enough, the same in not true for all. Then, the results from simulation are unreliable.

There ought to be a longer list of reasons, and I think other people would have more constructive inputs too.

Regards
Vivek

Hi,

I just would like to note that I'm not sure about the bad matching argument. The rule of thumb that current mirrors require a large Vgs-Vt
for good matching is derived from the (ideal) MOSFET square law, with the transistors in the saturation region. So, you can not make any
statements about the matching of transistors in another operating region (subthreshold), based on this derivation (albeit that you may, in the end, be right that subthreshold operation is bad for matching).

Kind Regards

Peter

Just to quickly address the matching issue.  If you do the math you get matching that is proportional to 1/(V_GS-V_T).  You cannot use this formula in Subthreshold!  Let me give you a rough formula assuming that V_T mismatches are dominant (please verify as this is off the top of my head).

σ(ΔI/I) ≈ 2σ(ΔV_T)/V_OD
where
V_OD = V_GS-V_T                  if V_GS-V_T > 2nU_T
V_OD =  2nU_T                     if V_GS-V_T < 2nU_T
U_T is the thermal voltage kT/q and n is a process parameter in the neighborhood of 1.3 to 1.8

So... the mismatch doesn't suddenly go through the roof, but if you were to choose an operating point you wouldn't want a mirror biased at ST if matching was important.  

Modeling issues may or may not be a big deal - be concerned if you need "absolutes" like gm to be spot on (for AC bandwidth), and especially if you have a circuit that depends on two mosfets operating at different current densities such as the ΔV_GS (constant gm) bias circuit.  But things like mirrors and diff pairs work fine in ST.

Leakage can be a very large source of error at hot if you are deep in ST.  

The performance versus operating point is a continuim.  I wouldn't arbitrarily decide a design is bad because it slips into ST on one corner, but I might wonder why my operating point is changing.

Vivkr, I agree that I wouldn't run a mirror in WI given a choice, but making the lengths longer is just going to slow it down even more....  I've been running mirrors and other devices in WI (from nA to mA), when appropriate, for a decade or more and the stigma asociated with WI simply isn't justified.  Nothing terrible is going to happen if you have to lower the overdrive to meet some other spec.

Back to the original question, as far as headroom is concerned, keep in mind you still need to keep Vds > ~100mV (at room) even if you are in WI.  There isn't much advantage in going deep into WI for headroom.