Without seeing the architecture you are using, it is somewhat hard for me to imagine why you are seeing some of the things you describe. You mention PMOS, so i assume you are using Miller compensation in which case no load & low ESR should be your worst case stability condition. It would be helpful if you post what test condition causes what PM or LG change, etc...
A fool proof way of checking stability is the transient load step test. Check how much is your maximum load current and use a pwl current source with a 1 ns rise and fall time and let it run long enough for the output voltage to settle after the overshoots subside. By looking at how much ringing you have you should get a good idea of how stable your loop is. Make sure you set your transient analysis tolerance to conservative.
AC simulations should correlate if you break the loop correctly and mimic all the necessary capacitances at the break point. If AC doens't match transient i'd believe transient analysis.

   Hi Smart,
      I would suggest a number of things:
1. Why do you need a 2-stage OTA? That leaves you with three gain stages counting the power PMOS, this is going to be difficult to compensate/stabilize and your open loop gain is pretty low for such a large amount of gain stages anyway. You could use a cascoded gain stage folded cascode and get as much gain as you get with the two-stage OTA. Then with Miller compensation you can easily split the poles of your two gain stage system. Since you don't have a load capacitor ESR either, you don't have a zero to try to help you compensating this system. Here you have no choice than to keep it simple to make your life easy.
   I think that your stability problems are probably due to the output node's impedance varying widely since the impedance of this node (when it is high) will give you a pole that will move towards lower frequency and it will be getting close to the other pole that is not being split by Miller comp in your 2-stage OTA.

First, since the LDO you are using is for the application of digital power supply, I think the setup with RL is more accurate. From my point of view, with the ideal current source , it is so strong that make the setup of DC operation point easier.  

Basiclly, I agree with the Raul that in order to make your life easy, it is better to use cascode or folded cascode structure instead of 2-stage OTA since you have to be very careful for the compensation of multistage amplifier.

For your circuit diagram, I will treat your 2-stage OTA just as an OTA block regardless of the detailed structure inside. Then, the diagram you shown is reduced to a two poles system. The output of OTA comtributes one pole, and the other is located in the output VREG2.4. Two-poles system is inherently not stable, this is why you add miller compensation capacitor to split the two poles. A left-hand plane zero is contributed by the compensation resistor and capacitor, this can help in keeping the phase margin.

For the tradiotional LDO design, large output capacitor is needed in order to stabilize the system, by which I mean that the dominant pole is situated at the output regardless of the load current. However, this is not the case in your circuit if not mistake. The 100p F is too small to make the output node dominant in all the range from 1uA to 8mA, this is not good for stability. What is more, the miller compensation cap is added to just make the output node of OTA more dominant. So, I assume that the dominant pole is at the output of OTA.

You mentioned that both setup 1 and setup 2 give very good PM. I think this is not surprise. since the dominant pole is situated in very low frequency(if you use the 2-stage OTA, then the output impedance of OTA would be very large, plus the big miller compensation capacitor, this pole is in very low frequency indeed). Hence, the consequence is to make these two poles well seperated and what's more, you have one left-hand plane zero to keep the phase. This is why you did not see any change from the frequency response when you tune the RL or IL in a large range.  If you reduce the value of miller compensation cap or increase the decoupling cap, you will see the difference.

For the setup 3 where you plug the inverters in, I am fine with the way you find the equivalent impedance. If not mistake, you swept the DC voltage of the input which comes from the LA(this equilatent to RL), and saw the frequency response. The weird thing you find is most probably due to that under certain condition, the LDO is out ot regulation , or in other word, the current vaule is beyond the current capability of the PMOS pass transistor. Suppose you have 100 milli ohm, then current being sink should be 2.4/(100*10-3)=24 Amp. This is huge !!! , indeed. Of cause, if you take 400 ohm, the sink current 2.4/400=6 mA, then this value is within the 8 mA specification of you LDO design.  

However, the problem with this setup 3 is that during switching or in transient simulation, the impedance change of the inverter is rather difficult and more than the way you use in setup 3 since it is a switch(characteristic of digital circuits). Pluging the inverter to find the frequency response ,that is nothing help. This accounts for why you  did not find any problem during the transient simulation while there is weird things with setup 3 frequency simulation, by which I mean setup 3 could not represent the real situation.  

what I suggest:

1.  RL and CL as load,
2.  make sure even in the worst case, you still have decent phase margin, just as Raul mentioned before. In your case, lowest current condition.
3.  The most important thing: do the transielant simulation with your real digital circuit. In your case, adding the cascaded inverters.

if these test all pass your sepcification, then it is ok anyhow.  

Hope this can help !  I would really like to discuss with you guys on this.  


taofeng

For the simple 2-stage LDO design , I think the simple miller compensation is good enough.

You do not have to worry about the weak-inversion effect, since it is normal that your PMOS pass transistor experiences the saturation, linear and sub-threshold regions with so wide variation in the load current. However, the advantage of making the PMOS pass transistor always in saturation is that it could ensure a high output impedance of PMOS, which is good for the PSRR, especially in high frequency.

What do you mean the CC compensation ?  if you mean only CC compensation (without compensation resistor RC), then most probably the zero in between the dominant pole and second pole is caused by the parasitic pole in side the folded cascode OTA. However, if you mean CC compensation with the compensation resistor RC, then the zero is caused by the CC and RC, which is very apparent.  

I do not know if I make it clear for you ?

Could you please attach some simulation results ?

best regards,

taofeng

Dear all,

Sorry i just have no idea how to attach 2 files in a post.

Here is the transient result.

regards,
Smart

could you also please tell how and where you cut the loop ?

Of cause, I mean open loop gain. In detail, I want to know the open loop gain/phase of the OTA (the first stage) and the open loop gain/phase @ VREG2.4 (which is the total gain of the 2-stage ), you can plot in the same graph.

Basically, I agree with you that no matter where you cut the loop, the simulation results would be almost the same. However, the traditional way is to break at the node beween resistive feedback and Vp of the OTA. By doing this, you can check the gain/phase of the first stage(OTA).

From your simulation above, I see that the overal gain is around 60dB if not mistake. However, you mentioned before also that the OTA itself gives 60dB, which means that your Pass transistor does not have any gain or the gain is so very low ? it is weird actually.

I would suggest the following things:

1.  pick-up the folded-cascode OTA only, and do the pole -zero(stability) analysis, by which I mean the open loop analysis.
2.  sweep the RL in a decent range, let's say 1k to 100k, and plot the gain/phase.
3.  increase the ramping up time from 10ns to let's say, 1us, just to see if there is any difference. Because 10ns is too fast to activate the loop(10ns means 100MHz bandwidth, it is impossible for your case with the miller compensation. From your simulation above, the bandwidth is from 2MHz to 25MHz, so take 1us as an example ).

hope this helps !

best regards,

Junfeng