Dear Jun Feng and uncle_ezra,


Thanks for your reply.

Let me answer the question before I ask something else.

From your simulation above, I see that the overall gain is around 60dB if not mistake. However, you mentioned before also that the OTA itself gives 60dB, which means that your Pass transistor does not have any gain or the gain is so very low ? it is weird actually.

In deed the OTA's gain is around 60dB, the total LG is around 60-80dB which is with feedback factor about 0.5 (-6dB).

you should really ask yourself that: which pole should be the dominant one ?

Before compensated, the dominant pole located at output of OTA, which is around 2kHz and the second pole at output which is around 500khz, PM is around 10 degree.

After putting CC=10pF, the dominant pole still at output of the OTA.


I would compensate either by adding ESR (if permitted) in the output so a zero is created or use NMOS or native NMOS (if available) as your pass transistor

I'm not allowed to use external cap, only internal 100pF is allowed. Using NMOS is possible, but can the OTA work with output range 2.4~ 3.0(with NMOS's Vth=0.6V and VDD=2.4V) at all corner (even VDD_Supply=3.0v)? Please share your idea.



Now is my turn to explain something i have discovered.

I have realized that that the Trans result i have shown early is due to a current surge from the inverter, this is due to Vcm of LA =1.2v, at some case, it caused the inverter change the oparating region, when VDD3.3 ramp up hence VDD2.4 also, this (current surge) cause the LDO operate unusually (the gate and drain of the PMOS raise at same time).

To solve this problem, I have put additional Rmin resitor at the VDD24D, to make sure the minimum amount of current sink from the Pass Transistor, now, the "oscillation" thing has gone, the trade of is additional static current. I have attach a graph, which is I give a current pulse (10us rise/fall time) at the VDD24D without connecting inverter (I call it setup 4). You can see when the although the VDD24 has already stable, when there is a large current rise/fall fast, the VDD24 will fall/rise, which is out of the regulation. Maybe this is one of reason, why usually LDO put a large capacitor externally to prevent spike, is it? Maybe someone can explain this?


Hope someone can help, Thank you in advance

regards,
Smart

Dear Jun Feng,

Thanks for quick response.

wheather or not out of regulation depends on you application, since this LDO is for digital power supply, then let's say within plus and minus 10% of 2.4V is tolerant. How is yours ?

As you can see from my previous transient simulation for setup3 (LDO with inverters, ramping VDD33), the VDD24 latch-up to about 2.8v, which is more than 10% of 2.4V.

Yes, for the traditioanl LDO design, large cap is needed to reduce the undershoot and overshoot during current ramp-on and off.

Do you mean spike?  

Do you mean you add additional resistor to sink some current in the start-up simulation ?

This additional Rmin resistor is to maintain a minimum amount of current sink from the PMOS, hence it will eliminate the large ouput impendance for low current load. This can prevent the ouput pole shifted to become dominant pole when low current load case. It's so far work for me, I will do more analyisis on this and tell u the details (this is one of the method written in a book).


you can achieve stability by increase the value of compensation cap instead of increasing the quiescent current.

I have tried a increase the CC to even 50pF, although AC analysis show good result (without inveters)  but still when comes to setup3 simulation, the "oscillation " still exist. At least so far adding the Rmin I see good result.

how is the problem with open loop simulation? I mean the strange zero ...

Sorry i haven't done this simulation. Can you please explain what is the setup for the open loop simulation?

How about your LDO design, any issue you face? Please share with me, maybe some hidden problems that i have not discovered


Best regards,
Smart

Dear Jun Feng,

Let me clarify the setup of the open loop before i do it later (next morning).

setup 5.

1. break the feedback point. VP and resistive feedback.
2. give the Vp=Vn=1.2v (default dc point)
3. give Vp, ac=1
4. do ac analysis
5.check  the open loop gain/phase of the OTA (the first stage) and the open loop gain/phase @ VREG2.4 (which is the total gain of the 2-stage )

is this what you wanna see?

regards,
Smart

I dont quite understand how you are breaking the loop. Usually you use a large inductor and capacitor together with an AC source to break the loop. The inductor is to provide dc bias while blocking the AC signal and the capacitor is used to couple the AC signal and block DC.

One other method is to use the iprobe in Cadence and run stability analysis. Either way works

Usually you use a large inductor and capacitor together with an AC source to break the loop. The inductor is to provide dc bias while blocking the AC signal and the capacitor is used to couple the AC signal and block DC.

Yes, this method is so-called Middlebrook.

One other method is to use the iprobe in Cadence and run stability analysis. Either way works

I prefer this method (and I'm using it for stability check), someone has mention "iprobe" provide slightly better accuracy.

Regards,
Smart

would it be nice to post the simulation ?  

plot the gain/phase @  output of OTA  and @ VREG2.4

annotate what is the load condition.

good luck

Dear Jun Feng,


BW=5.4k is the first dominant pole ?
Ro=2.4Mohms is the output impedance of OTA or your RLoad ?

It's the BW and R0 of the OTA, which is the frequency response at the output node folded-cascode.

how come the total gain of the two stages becomes only 15dB ? it is too small, at least larger than 40dB. It is not good design at least in the load condition, what is your load in this case ? try to tune some parameters, I think the size of PMOS pass transistor is too small if not mistake ?

THe Load is RL which connecting inverters. The reason behind this is , I open the loop an give vn=vp=1.2v, and vp ac=1, the loop now is completely open, there is no feedback which is adjust the dc point. the current flow tru the PMOS is around 130uA and VDD24 =135uA * 24k=3.28v and the PMOS has gone to linear region, which then provides small gm. (It won't happen like this in actually circuit with feedback, the PMOS will be always in saturation).


Do you have to make sure all the MOS still in saturation even in open loop circuit?


Regards,
Smart

Your loop gain is too low. Please check your DC operating point and make sure your PMOS is in saturation.

The loop gain equation is gm1*R1*gm2*Z*R1/(R1+R2)