always@smart
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ASIA
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Dear Jun Feng and uncle_ezra,
Thanks for your reply.
Let me answer the question before I ask something else.
From your simulation above, I see that the overall gain is around 60dB if not mistake. However, you mentioned before also that the OTA itself gives 60dB, which means that your Pass transistor does not have any gain or the gain is so very low ? it is weird actually.
In deed the OTA's gain is around 60dB, the total LG is around 60-80dB which is with feedback factor about 0.5 (-6dB).
you should really ask yourself that: which pole should be the dominant one ?
Before compensated, the dominant pole located at output of OTA, which is around 2kHz and the second pole at output which is around 500khz, PM is around 10 degree.
After putting CC=10pF, the dominant pole still at output of the OTA.
I would compensate either by adding ESR (if permitted) in the output so a zero is created or use NMOS or native NMOS (if available) as your pass transistor
I'm not allowed to use external cap, only internal 100pF is allowed. Using NMOS is possible, but can the OTA work with output range 2.4~ 3.0(with NMOS's Vth=0.6V and VDD=2.4V) at all corner (even VDD_Supply=3.0v)? Please share your idea.
Now is my turn to explain something i have discovered.
I have realized that that the Trans result i have shown early is due to a current surge from the inverter, this is due to Vcm of LA =1.2v, at some case, it caused the inverter change the oparating region, when VDD3.3 ramp up hence VDD2.4 also, this (current surge) cause the LDO operate unusually (the gate and drain of the PMOS raise at same time).
To solve this problem, I have put additional Rmin resitor at the VDD24D, to make sure the minimum amount of current sink from the Pass Transistor, now, the "oscillation" thing has gone, the trade of is additional static current. I have attach a graph, which is I give a current pulse (10us rise/fall time) at the VDD24D without connecting inverter (I call it setup 4). You can see when the although the VDD24 has already stable, when there is a large current rise/fall fast, the VDD24 will fall/rise, which is out of the regulation. Maybe this is one of reason, why usually LDO put a large capacitor externally to prevent spike, is it? Maybe someone can explain this?
Hope someone can help, Thank you in advance
regards, Smart
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