taofeng
Junior Member
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Posts: 22
Belgium
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First, since the LDO you are using is for the application of digital power supply, I think the setup with RL is more accurate. From my point of view, with the ideal current source , it is so strong that make the setup of DC operation point easier.
Basiclly, I agree with the Raul that in order to make your life easy, it is better to use cascode or folded cascode structure instead of 2-stage OTA since you have to be very careful for the compensation of multistage amplifier.
For your circuit diagram, I will treat your 2-stage OTA just as an OTA block regardless of the detailed structure inside. Then, the diagram you shown is reduced to a two poles system. The output of OTA comtributes one pole, and the other is located in the output VREG2.4. Two-poles system is inherently not stable, this is why you add miller compensation capacitor to split the two poles. A left-hand plane zero is contributed by the compensation resistor and capacitor, this can help in keeping the phase margin.
For the tradiotional LDO design, large output capacitor is needed in order to stabilize the system, by which I mean that the dominant pole is situated at the output regardless of the load current. However, this is not the case in your circuit if not mistake. The 100p F is too small to make the output node dominant in all the range from 1uA to 8mA, this is not good for stability. What is more, the miller compensation cap is added to just make the output node of OTA more dominant. So, I assume that the dominant pole is at the output of OTA.
You mentioned that both setup 1 and setup 2 give very good PM. I think this is not surprise. since the dominant pole is situated in very low frequency(if you use the 2-stage OTA, then the output impedance of OTA would be very large, plus the big miller compensation capacitor, this pole is in very low frequency indeed). Hence, the consequence is to make these two poles well seperated and what's more, you have one left-hand plane zero to keep the phase. This is why you did not see any change from the frequency response when you tune the RL or IL in a large range. If you reduce the value of miller compensation cap or increase the decoupling cap, you will see the difference.
For the setup 3 where you plug the inverters in, I am fine with the way you find the equivalent impedance. If not mistake, you swept the DC voltage of the input which comes from the LA(this equilatent to RL), and saw the frequency response. The weird thing you find is most probably due to that under certain condition, the LDO is out ot regulation , or in other word, the current vaule is beyond the current capability of the PMOS pass transistor. Suppose you have 100 milli ohm, then current being sink should be 2.4/(100*10-3)=24 Amp. This is huge !!! , indeed. Of cause, if you take 400 ohm, the sink current 2.4/400=6 mA, then this value is within the 8 mA specification of you LDO design.
However, the problem with this setup 3 is that during switching or in transient simulation, the impedance change of the inverter is rather difficult and more than the way you use in setup 3 since it is a switch(characteristic of digital circuits). Pluging the inverter to find the frequency response ,that is nothing help. This accounts for why you did not find any problem during the transient simulation while there is weird things with setup 3 frequency simulation, by which I mean setup 3 could not represent the real situation.
what I suggest:
1. RL and CL as load, 2. make sure even in the worst case, you still have decent phase margin, just as Raul mentioned before. In your case, lowest current condition. 3. The most important thing: do the transielant simulation with your real digital circuit. In your case, adding the cascaded inverters.
if these test all pass your sepcification, then it is ok anyhow.
Hope this can help ! I would really like to discuss with you guys on this.
taofeng
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