Hello everyone,

  Hope can get you guys help. Thanks in advance,

As you can see from this circuit diagram, this is basically a LDO design for the application of digital power supply.

Gm: the transconductance of OTA
Caux: Compensation cap 20p F
Raux: Compensation resistor, around several K ohm
gm: the transconductance of Pass transistor
CL: Load capacitance, around several pF
RL: Load capacitance, from 300-30k ohm
Cdecouple: tank or decoupling cap, 100p F which is internal. No
external big capacitor are allowed to use

I do not want to talk about the stability issue since it is straitforward and assume you guys all know it very well. However, I want to do some interesting things:

I introduce some AC current noise @ the output, and obeserve the current change @ the VDD supply. Then I define a current transfer function as H(S)=Ivdd(s)/Inoise(s). This function reveals that how the VDD can suppress the di/dt induced by the input noise. The poles and zeros are shown in the first graph. The simulation of the H(S) is shown on figure 2, basically this is a low pass filter which is apprarent.

However, from simulation, I find there is always peak. This is due to the fact that the zero is tracking the dominant pole, the consequency is to make the second dominant pole the -3dB (or cut-off) frequency. Or in other word, the cut-off frequency is shifted to higher frequency, which sacrifices dynamic noise performance. !! My goal is to make the dominant pole the cut-off frequency. !!

I also find that this phenomena is intrinsic to this feedback topology, by which I mean this zero and dominant pole are exactly the same after approximation(located in the GBW of the OTA).

I do not know how to solve this problem. Probably there are some options to do it: 1. kick out the zero ? this leads to the stability problem 2. make the dominant zero and pole well seperated. ... But I can not figure it out yet.

Hope I make myself clear, and hope some one can help me out !!!

thank you in advance!

taofeng