Hi all
I have set-up a mixed-mode test bench containing digital blocks with "functional" views. Simulation ends up successfully but all outputs of the digital blocks are zero and it seems that it is not working at all, (The schematic views of these digital cells work fine in an ordinary simulation). I also see the following note on my CIW:
"*** NOTE: You have selected to instantiate behavioral/functional module explicitly.
   This will cause problems if the behavioral/functional module has ports that are
   declared just by a port expression having bit select or part select of a vector
   or bundles/concatenations of nets."
Actually I don't get the meaning of this note. Is the problem related to this note? How I can fix it?
Could be other problem involved?

Regards
Hamed

Thanks Andrew,
Actually I have been using SpectreVerilog. I have checked all signals arround, but it seems that a functional block doesn't work at all.
I haven't been able to use AMS because some problems in our environment settings.
As I do continue to make AMS operational, I would appreciate if you tell me how AMS can help if SpectreVerilog can not recognize/deploy the functional block?
Is there any possibility of having bugs in SpectreVerilog?

Hamed