In 130nm cmos process, the supply voltage will be as low as 1.0v ± 10%. So, the worst case supply will be 900mV.

chip's output is differential, CML style signal and AC coupling is used. CML output driver is required to have swing as high as 900mVp-p.

Is that possible to be implemented without additional high supply voltage?

I do not think it is possible, since the output common mode will be as low as "900mV-450mV=450mV". And, when output reach max swing, the low output node will be as low as "225mV". That is too low. Tail device might fall out saturation, or output impedance will be distorted.

What's the real story behind those serdes products?

what if the AC coupling capacitor is used?

thus there is only near-end 50ohm resistor works as pull up resistor.

i guess you are not familiar with that circuit style. Let me just elaborate.

There are totally four 50ohm termination resistors as pull up. Two at the near end and two at the far end.
However, far end pull up resistors are isolated from near end output by a 100nF capacitor. That's called ac coupled double termination.

The problem is very real.  If your return loss can afford, you can source two common mode currents into the outputs wwith two pmos sources.  They will have to be rather large to keep them in saturation, that's why I mentioned the return loss.  This way you can alleviate the headroom for the diffpair, but you cannot pull up your common mode all the way to 900m-225mV.

You can relay on a higher supply just for the common mode shift.

Or you can use voltage driver.  900mVppd would be the maximum from that.  No margin left though.

Zoltan

LE:

What you mentioned is LVDS style dirver, with termination. Is that type of driver used broadly in the industry?
There is rumor saying that its signal integrity is not that good. But due to its low power nature and cmos direct drivability, a lot of temptation to use that.


loose-electron wrote on Aug 4^th, 2006, 10:00am: