shpongle
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Posts: 3
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Hi,
I need to have a rough estimation of the equivalent number of gates required to design a decimator for a delta-sigma converter. Is there any "good practice rule" which gives an estimation of the number of equivalent gates based on the filter order, word length, ... ? or do I have to size the decimator i.e. partition into 2-3 decimation stages, specify each filter, write some verilog/vhdl and ask an EDA synthesizer tool for the estimation of gates using NAND logic ?
Any hints, information is welcome and greatly appreciated
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