always@smart wrote on Jun 1st, 2006, 8:45am:Thanks ACWWong,
can you please describe in more detail:
the common-emitter (common-source) of a long tail pair will give you a rectified version of the input
Is it a peak detector, which a long tail paraller with a cap to abstract the peak here? But how can it mentain the same peak with PVT change of the input NMOS pair?
Regards,
Smart
Basically I mean you use the full wave recified signal at the common-source node of NMOS pair (at the current source drain), feed that into a comparator to get an input signal dependant current output, which is then summed in cap, and compared with a reference voltage. But as you said to guarantee the 100mV input signal trip point accurately is tricky over PVT (The last time I designed something like this, i used some TRIM bits and a calibration routine...)
Anyway another way as mikki has suggested in the multplier apprach, but I would also try the unbalanced source coupled pair rectifying transconductor as used by the references below:
http://eceserv0.ece.wisc.edu/~sharmav/bluetooth/PowerAmp.pdfp19 has the unbalanced source soupled pair approach
p18 has the multiplier appraoch.
A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs
Kimura, K.; Solid-State Circuits, IEEE Journal of , Volume: 28 Issue: 1 , Jan. 1993
A 450MHz CMOS RF Power Detector: Stacy Ho. RFIC symposium 2001.
Finally may I add accurate signal level detection @1.25Gbps @ <20uA sounds VERY tough... even in super fast 0.13um CMOS.....