Designer’s Guide Community

baohulu Community Member Offline Posts: 43 china	clock in the SC-CMFB of the opamp in pipelineADC Jun 14^th, 2006, 9:35am hi, in my design of pipeline ADC, I choose a common used SC-CMFB for my opamp, but I am not sure whether the clock of the SC-CMFB of the opamp is the system clock of the pipeline ADC for example, if my pipeline ADC is 100MSampling/s, then do I need to set my clock of the SC-CMFB of the opamp as 100MHz
Back to top	IP Logged

Sid

Community Member

Offline

Posts: 35

Re: clock in the SC-CMFB of the opamp in pipelineA
Reply #1 - Jul 22^nd, 2006, 9:23am

Sorry that you are getting a delayed answer for your question. The answer is typically YES. This is because the OTA does nothing during one half cycle and hence you can use fCMFB = fpipeline. For eg, when stage 1 samples the signal the OTA is not used and can hence be connected to the CMFB capacitors. During hold, the OTA is in amplify mode.

However, if your pipe is using OTA sharing between stages, this may or may not be possible and you may have to be more careful.

Hope this helps,
-Sid

Back to top

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: clock in the SC-CMFB of the opamp in pipelineA
Reply #2 - Jul 31^st, 2006, 5:56am

Sid wrote on Jul 22^nd, 2006, 9:23am:

For eg, when stage 1 samples the signal the OTA is not used and can hence be connected to the CMFB capacitors. During hold, the OTA is in amplify mode.

Hope this helps,
-Sid

Hi Sid,

This sounds dangerous to me. If I understand correctly, you are suggesting that the CMFB loop be broken during the amplification phase. That would not help much as this is the time when the CMFB should really be doing the job of controlling the CM levels. Improper or missing CM control can be fatal to circuit operation and performance.

Perhaps you mean something else.

Regards
Vivek

Back to top

IP Logged

ywguo

Community Fellow

Offline

Posts: 943
Shanghai, PRC

Re: clock in the SC-CMFB of the opamp in pipelineA
Reply #3 - Aug 1^st, 2006, 7:02pm

Hi, all,

The clock of SC-CMFB is always non-overlapping clock, the same as the non-overlapping clock for sample and hold. However, it doesn't matter that the CMFB cap should be tied to the opamp output at sampling phase or hold phase. In a pipelined ADC with amplifier sharing, the CMFB cap is tied to the opamp output at stage1's sampling phase and stage2's hold phase, or vice versa. So don't worry about it.

BG
Yawei

Back to top

IP Logged