HI,
if I design a 100MS/s pipelined ADC, and I use a opamp with a SC-CMFB, should I choose the clock of the SC-CMFB as 100MHz?
if it is sure. because the common used 6_switched_4_capacitors SC-CMFB can be equavilent as a switched resistor, with a value having the order of 1/(fclk*C), so if the fclk=100MHz, if I want to get a high switched resistance, say 100K, I have to choose the capactior value as 1/(100M*100K)=100fF, and this resistance is paralleled with the output resistance of opamp. so if I want to get a high gain, I need high output resistance , thus high the switched resistance, thus a much smaller capacitor in the SC-CMFB, right? but if the capacitor of the SC-CMFB goes too small, can it kick the disturbance of the paracitic capacitors?

regards