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Faisal

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Verilog-A vs Verilog AMS
Jun 23^rd, 2006, 7:53am

Hi,

I intend to simulate my design in a combination of ideal components available in analogLib and models other in an Analog HDL language. There seem to exists a plethora of languages for the modeling and I am not sure which one is worth to learn.

I would prefer some flavour of Verilog for analog modeing, as I am relatively fluent in this language as compared to VHDL (digital domain). Kindly suggest.

Faisal

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Eugene

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Re: Verilog-A vs Verilog AMS
Reply #1 - Jun 23^rd, 2006, 1:28pm

The analog behavioral modeling languages I know of are:

VerilogA
VerilogAMS
VHDLA
SpectreHDL
MAST
C
Matlab

In composing the above list, if the "language" was supported by an analog circuit simulator, I considered it an analog behavioral modeling language. I included C because I believe IsSpice lets you write your own models in C. I included matlab because I believe at least one circuit simulator lets you include matlab models. C and matlab are more general than the others in that they do not have functions like "@cross" or "@timer" or "transition" that are peculiar to analog circuit simulation. But I suspect you already know those languages anyway.

Each of the languages probably have their unique advantages and disadvantages. If it were me, I would not base my decision so much on the language itself but rather on the larger tool picture. For example, if you are using Cadence tools, I would go with VerilogA or VerilogAMS because the Cadence mixed signal environment was designed around those. If I were going to use Synopsis tools, I might go with MAST and the Saber simulator. My point is that I think you should select the tool that best suites your larger needs and then learn the language that comes with it.

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Faisal Community Member Offline Posts: 90	Re: Verilog-A vs Verilog AMS Reply #2 - Jun 26^th, 2006, 5:20am Thanks, I am using Cadence tools so the choice narrows down to Verilog-A vs Verilog-AMS, I guess. Is Verilog-A a subset of Verilog-AMS ??
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Eugene

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Re: Verilog-A vs Verilog AMS
Reply #3 - Jun 26^th, 2006, 8:49am

VerilogA and Verilog are supposed to be subsets of VerilogAMS. I have not tried to import a lot of Verilog code into an AMS simulation but from what I've seen, Verilog is indeed a subset of VerilogAMS. I have written a substantial amount of VerilogA code and for the most part, I have found VerilogA to be a subset of VerilogAMS. However, there are a handful of things I can do in VerilogA that I cannot reliably do in VerilogAMS. For example, I encounter AMS problems when I try to structurally instantiate one VerilogA module in another. We will probably need help from Cadence to figure that one out. The parts of VerilogA that are not supported in VerilogAMS are few and subtle but can take weeks to find. Such problems usually occur when you develop a model in VerilogA only, and then try to import it into the AMS environment. If you develop your models in AMS from the start, you spot the problems as they occur and thus have an easier time isolating them. The work-arounds are usually simple and sometimes amount to a simple syntactical fix. This one may have been fixed by now but at one time, something like x = (a+b) would work but x=((a+b)) would not. The extra paranthesis might arise out of a sequence of modeling experiments. But to be fair, it's been six years since I encountered the parenthesis problem and it might very well be fixed by now.

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Geoffrey_Coram

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Re: Verilog-A vs Verilog AMS
Reply #4 - Jun 27^th, 2006, 6:56am

Eugene wrote on Jun 26^th, 2006, 8:49am:

The parts of VerilogA that are not supported in VerilogAMS are few and subtle but can take weeks to find.

Per the language reference manual, Verilog-A is a subset of Verilog-AMS. What you are really saying is that your VerilogAMS simulator is not fully compliant with the Verilog-AMS LRM.

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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Eugene Senior Member Offline Posts: 262	Re: Verilog-A vs Verilog AMS Reply #5 - Jun 27^th, 2006, 8:06am Geoffrey, Thanks for pointing out my misleading statement. You have a valid and very important point. The reason these rare incompatibilities take so long to isolate is exactly because the language reference manuals say one thing but the simulator does another. -Eugene
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Faisal Community Member Offline Posts: 90	Re: Verilog-A vs Verilog AMS Reply #6 - Jun 27^th, 2006, 9:04am Thank you all for the information. I have anothe related question now. Is it possible to do Verilog (Digital design e.g. State machine, arithmetic) blocks from within Verilog A and/or Spectre ?? Is this recommended/followed practice ?? Are there any other simple alternatives ??
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Geoffrey_Coram Senior Fellow Offline Posts: 1998 Massachusetts, USA	Re: Verilog-A vs Verilog AMS Reply #7 - Jun 28^th, 2006, 5:03am Since Spectre is an analog simulator, I wouldn't expect to be able to do digital things in it. In the AMS LRM, Annex C.6, is the statement "No digital behavior or events are supported in Verilog-A."
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jbdavid

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Re: Verilog-A vs Verilog AMS
Reply #8 - Aug 3^rd, 2006, 5:37am

Eugenes problem doesn't apply GENERALLY to Verilog-A models in Cadence's AMS Designer, its only a problem for Verilog-A Models called from the the spectre model files. and it just takes a little restructuring to pull the resistors/ diodes capacitors OUT of a verilog-a structural model into a subcircuit that calls that verilog-A model.. and this is one area where only the Verilog-A subset can be used..
Ie the model files have to work with spectre as well as with AMS designer..( and this might already be fixed - last time I had to fix this type of situation was about a year ago..)

When you get to the CIRCUIT LEVEL behavioral modeling, (veriloga views for circuit where you have a schematic ) The difference is that veriloga views (which can have structural as well as behavioral elements will work in Spectre (analog simulations) as well as Verilog-AMS (AMS DESIGNER) simulations..

AMS designer can handle both Verilog-A subset and Verilog (ie GATE, BEHAVIORAL or RTL) models.. But spectreVerilog could do that also..
What Verilog AMS gives you is the abilty to write MIXED SIGNAL models .. so that the ADC model has analog input connections from the "spice" side of the circuit, but LOGICAL output pins for the converted value, and a logical input pin for the clock.. if this Clock is one of the high speed signals in your circuit, it will dominate the spectre simualation.. but since its Logic in the AMS simulation, the model of the ADC is event driven, and actually uses an interpolated value of the input signal allowing only the filter in front to determine the analog solver's timestep.
In a Functional verification environment this gets you the SAME functional behavior (voltage converted to bits) at potentially 50-1000x shorter simulation times... which means you can actually check ALL the control signals.. (Powerdown, enable, select Ain, selectBin ....and maybe use a verilog model of the dsp as well..

In a PLL circuit I worked with recently I was able to watch the PLL lock in a few minutes compared to hours watching it get close to lock with VerilogA behavioral models.. just by keeping the output of the VCO, and clock divider and input to the Phase detector in the Logic domain.. It does take the equivalent of 3 spectre licenses though..

The other advantage is that now I ALSO have all the power of ncsim.. including VHDL, VHDL_AMS support for IP, transaction based verification approaches VPI, and PLI integration, SystemC , PSL assertions (but only for the digital side right now) .

but a little partitioning of your design can minimize the need for real mixed signal simulations..
If all the control bits are coming from a register bank and are essentially static, you can write a simple verilogA model to drive the whole set, and you might not even need to simulate any control bit transitions..
in fact to support this case, I've got perl scripts to generate the stimulus block model, the verilog stub model (gets me a symbol) and the testbench and then import (verilogin) the testbench and stimulus block..
It worked fine on one recent tapeout of mine where the digital to analog interface was very clean..
I only had 1 set of 5 control bits that I had to worry about transitions on, and verilog-A was sufficient for that as well.. (testbench) ..
but we have a dedicated systems team doing all the "full chip" behavioral modeling in matlab too..
(not linked to any actual schematics though)

AMS designer does have a way to link matlab models in also..
Hope this helps.

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jbdavid
Mixed Signal Design Verification

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