Hello all,

I am in a FPGA design class right now, and our VHDL/Verilog class is not listed as a prereq, but we have to code with it, so I'm stuck with a rather trivial problem.

It's a simple low pass filter, and Xilinx and Icarus alike tell me something along the lines of y not being a register. Perhaps you could tell me what is wrong, and maybe point out some things I did poorly in the code? Thank you very much.

Code:

module filter(clk,x,y);
    input clk;
    input [7:0] x;
    reg [15:0] stage1;
    reg [15:0] stage2;
    reg [15:0] stage3;
    wire carry2;
    wire carry3;
    wire [15:0] a1;
    wire [15:0] b1;
    wire [15:0] b2;
    wire [15:0] sum2;
    wire [15:0] sum3;

    output [7:0] y;

    initial
	begin
	  stage1 = 16'b0;
	  stage2 = 16'b0;
	  stage3 = 16'b0;
	end

    always @ ( posedge clk )
	begin
	  mult_const_b1( y, b1 );
	  add16( stage2, b1, 0, sum3, carry3 );


	  mult_const_b2( y, b2 );
	  add16( stage1, b2, 0, sum2, carry2 );

	  mult_const_a1( x, a1 );

	  assign stage1 = a1;
	  assign stage2 = sum2;
	  assign stage3 = sum3;

	  assign y[7:0] = sum3[15:8];
	end

endmodule 

Ok, so when you say it will have that value for all time, it will also change with its value as well, hence the block that just changes the register?

Also, you were corect about the const functions. They are just functions which multiply the operand by a certain constant needed for my filter.

I redid the code, and got it to compile like this:

Code:

module filter(clk,x,y);
    input clk;
    input [7:0] x;
    output [7:0] y;

    reg [15:0] stage1;
    reg [15:0] stage2;
    reg [7:0] y;

    wire carry2;
    wire carry3;
    wire [15:0] a1;
    wire [15:0] b1;
    wire [15:0] b2;
    wire [15:0] sum2;
    wire [15:0] sum3;



    initial
	begin
	  stage1 = 16'b0;
	  stage2 = 16'b0;
	  y = 16'b0;
	end

    always @ ( posedge clk )
	begin
	  mult_const_b1( y, b1 );
	  add16( stage2, b1, 0, sum3, carry3 );


	  mult_const_b2( y, b2 );
	  add16( stage1, b2, 0, sum2, carry2 );

	  mult_const_a1( x, a1 );

	  assign stage1 = a1;
	  assign stage2 = sum2;
	  assign y = sum3[15:8];
	end

endmodule