I am just starting to do mixed-mode top level simulation in AMS using Cadence environment.
I am interested in the following methodology:

1) Creat config view using Hierarchy editor. For every block I will selecting either a AMS model, transistor level model or verilog-A model.

2) Once I have created the config view, I want to netlist this particular config view into a AMS (or any other appropriate ) netlist.

3) I want to instatiate the above netlist in my testbench which is written in AMS language (NOT a schematic).

4) Use ncverilog (or any other appropriate simulator) to simulate the above AMS testbench.

5) Once simulated I want to use AWD viewer in cadence to view the result.

Here are my questions:

1) Once I create the config view, how do I create a AMS netlist of the whole hierarchy ?

2) If I am compiling my testbench in command line, how do I include the connect modules ?

3) If I use ncverilog to compile the AMS testbench, is it possible to use AWD to view the result ?

I am in severe time crucnch, any help will be greatly appreciated.

Thanks
Saroj Rout
Analog Designer