This is just a guess:

Vbe=Vt*ln( I/(Is*A) ), so the larger the device is, the less the area variations will affect Vbe; you get a better-defined Vbe for a given I.

Hi,

Above reasons seem reasonable to me.

But now, I was told that it is mainly to reduce the base resistance, which is large for vertical PNPs of CMOS technology. If so, it's not clear to me 'how high base resistance will affect the bandgap performance?'.

Any idea?

I think there is a number of considerations here.

First and most practicle is what transistor (model and layout) you are getting from the foundary with the design kit.
I still remember times when the only one was 10X10. Now you may have others like 5X5 and 2.5X2.5. If your drsign was originated some time back and was silicon proved in previous processes (like 1 μm, 0.5, 0.35, 0.25 etc), why to change?

2. The β of parasitic bipolar transistor is very low and varies with I_CE. The β graph has some bell like curve, where the maximum is the preffered operating point. For small transistors, current which gaves max β may be low (let's say 1-3 μA), so you band-gap will be very mismatch sensitive. If you operates your band gap with higher currents, it will not be the band gap which your are expected to see, it will have too steep temperature curve.

3. R_b is also playing the role here. If you have small transistors, ratio of parasitic R_b and your designed resistor are growing and reducing you band gap abilities (more steap curve, more PVT sensitivity, more wafers/lots statistical spread). It is interesting to note that some time back for one of my previous emloyers I designed the small circuit to compensate R_b influence and R_b variation...

Hope, this explains something,
Michael

Thanks Michael, for your very detailed answer. But few things are not clear to me. Can you please explain?

1.  Why do we need to bias a BJT at high β? Since in a CMOS bandgap emitter current and not the collcetor current
is used to obtain ΔVBE, I think, β value should not matter.
However I think, low β coupled with high RB might cause some problem as vb of two BJTs
will not be at zero and MAY not be EQUAL. Am I right?

2. I have checked RB, RE, and RC values for 2X2um, 5x5um and 10X10um BJTs of 0.15um TSMC technology.
To my suprise I found that RB and RC values are almost same for all, though RE decreases as the size increases.
I think, thus one is not getting any benifit by going to high area from Rb perspective alone.  

3. I am eager to know the method to compensate Rb effect. Can you please
post it?

jcpu2006 wrote on Jul 2^nd, 2006, 10:57pm:


Larger R_b means larger variation of the difference of R_b and R_b/10 (if you are using 1:10 transistors ratio). That means ΔV_be varies more. And your band gap voltage depends more on doping density which is the changing process parameter. (different wafers and different lots)

ywguo wrote on Jul 3^rd, 2006, 7:27pm:


It may be the currents variations or your band gap has poor PSRR.
Also it may be worth to check your BJT work point from β point of view...
Does your bipolar transistor has typical/fast/slow model? If it is not, the situation on the silicon will be worse.
In this case you have to "create your own" fast and slow models (all parasitic resistors and β)

You don't say what large is.... it seemed 20x20 um^2 used to be the standard.  This is way bigger than necessary for matching and just about anything else.  The only reason you needed to use that big of a device was because it was the only one that had a model... which is often the case unfortunately.  

Smaller dimensions work better all around... they have lower Rb for a given area (i.e. you obtain better performance by putting 10 4x4 devices in parallel instead of one 20x20).

rg