I would guess that a 5x5 device will have an mismatch standard deviatoin on the order of 50uV.  That is a very rough number that ignores  contact resistance, etc.... I hate to even throw that number out... but the reason I mention it is because it may be significant depending on how you manage the other offsets, most importantly, the opamp offset.  Keep in mind that your overall size may be determined by diffusion spacings and not emitter area.

Bipolars don't scale perfectly.  You can't expect a 4x4 to behave like four 2x2s even though they have the same area.  Smaller area emitters generally result in lower Rb, which means you can run them at a higher current density, which means you'll have a bandgap with less noise.  This effect may be pretty small, though.

Bandgap references need a very accurate model.  The best bet is to use a device that has some history even if it costs you some area.  The reasons for this is the devices are notoriously hard to model.  If the device does have a good history, consider running it at the same current density.  A lot of bandgap errors occur because the device is run at too high a density so that base resistances and other non-ideal (read poorly modeled) effects contribute overly to the response.

If you don't have a history, or feel you can endure the wrath of your boss for not using a device with history, the best bet is to look at the performance verus current density rather the model parameters which often don't mean much (plus I can't rattle off the important non-ideal ones).  To do this, set up an experiment with your various bipolars, each with your desired ratio (e.g. 8:1).  As you know, the difference in emitter voltage should be U_T*ln(8) no matter what the current is.  Well, sweep the current and watch how that voltage behaves as current increases.   You can judge how much current you can run those devices and still be pretty ideal.  I generally run them at the point where the votlage changes a few hundred uV above the ideal value.

PS, I made an error in my previous post when I said 10 4x4 devices instead of a 20x20.  It should have been 25 4x4 devices since that ill give the same area.  

rg

ipsc,

There are some good tutorials on www.circuitsage.com.


Yawei

Let me note a key thing here: CMOS bandgaps.

That means that you are probably using the collector tied to substrate PNP that is available on P Substrate, single N-well CMOS.

That is a lateral PNP which in addition to having terrible Ft and terrible Beta, it is very resistive. If you get a model that accuratly reflects the resistances inherent to the junctions, you see that you need to keep the currents low, or the junction areas high for the body resistance to not play into the Vbe differences between the large and small junction areas.

A good example of this is the thermal monitor that gets used in all Intel processors. It is monitoring the Vbe of a diode junction on the microprocessor. Due to all the resistance, the external thermal control chip that uses this diode keeps the currents between 10uA and 100uA, otherwise the resistance gets into the equation a bit too much. (starts looking like V=IR instead of V = Vbe)

Big thing in CMOS bandgaps tends to be mismatch of the differential pair in the bandgap amplifier. That tends to dominate the erros of the device. COnsider chopper stabilization or an offset alignment to work around that.

my 2 cents worth...