When building an antenna in VerilogA, the simulation work for tran, ac and sp, but for pss, spectre indicates a hidden state of the variables L and C.

The antenna has an available power (receiving a signal at a certain frequency) and an impedance. The impedance is determined by the magnitude and angle of the reflection coefficient. In this way, a constant magnitude and swept angle represents all impedances that a circle with constant radius passes through in the smith chart. (A circle in the Smith chart corresponds to a constant VSWR value).

With this construction of the antenna, depending on the value of the angle, the impedance should be represented by a capacitor (lower part of Smith cart) or an inductor (upper part of Smith chart) in series with a resistor and a voltage source. I have put the inductor and capacitor in parallel and the angle determines which is conducting.

I have tried to "activate" the L and C for every timestep but, perhaps, since the angle is independent of the time it has not been a success.

Any ideas how to solve or completely eliminate the hidden state problem?  


// VerilogA for DVBUnitcells, Antenna, veriloga

`include "constants.vams"
`include "disciplines.vams"

module Antenna(v_ref, feed);

inout v_ref, feed;

///////////////////////
// v_ref is ground.
// between ground and v is a voltage source v_source
// between v and res is a resistor with value R
// Between the resistor and the antenna feed is a capacitor or a inductor.
//////////////////////

electrical  v_ref, v, res, feed;      

parameter real AvailablePower_dBm = -50 from (-inf:inf);
parameter real Magnitude = 1m from [0:1);
parameter real Angle_rad= 1m from [0:6.2832];
parameter real Frequency = 1G from (0:inf);


//local variables
real AP, mag, ang, f, v_source, R, L, C, pi ;


analog begin

pi=3.14159265358979323846264338327950288419716939937511;

AP  = AvailablePower_dBm;
mag = Magnitude;
ang = Angle_rad;
f   = Frequency;

if (mag == 0) begin
mag = 1n;
end

if (ang == 0) begin
ang = 1n;
end

if (ang>6.2831) begin
ang = 6.2831;
end


if (ang>3.1415 && ang<3.1416) begin
ang = 3.1415;
end


// x^y is in Skill x**y but in VerilogA pow(x,y).

 v_source = sqrt(1E-3*pow(10,(AP/10))
     *8*(-50*(-1+pow((mag*sin(ang)),2)+pow((mag*cos(ang)),2))/
     (1+pow((mag*sin(ang)),2)-2*mag*cos(ang)+pow((mag*cos(ang)),2))));

 R = -50*(-1+pow((mag*sin(ang)),2)+pow((mag*cos(ang)),2))/
     (1+pow((mag*sin(ang)),2)-2*mag*cos(ang)+pow((mag*cos(ang)),2));

     // Inductor and capacitor is parallel
     // but given values in a way that only one is conducting current

 if (ang<=3.1415) begin      // Inductor
   L =100*mag*sin(ang)/((1+pow((mag*sin(ang)),2)-2*mag*cos(ang)+
     pow((mag*cos(ang)),2))*2*pi*f);
   C = 1a;      //small but nonzero
 end

 if (ang>=3.1416)      begin            //Capacitor
   C = 1/(2*pi*f*(-100*mag*sin(ang)/
     (1+pow((mag*sin(ang)),2)-2*mag*cos(ang)+pow((mag*cos(ang)),2))));
   L = 1;      //Large
 end


V(v,v_ref)   <+ v_source*sin(2*pi*Frequency*$abstime);
V(v,v_ref)   <+ ac_stim("ac",v_source);            //  ac only
V(v,v_ref)   <+ ac_stim("pss",v_source);            //  pss only
V(v,v_ref)   <+ ac_stim("sp",v_source);            //  sp only
I(v,res)     <+ V(v,res)/R;
I(res,feed)  <+ idt(V(res,feed)/L);
I(res,feed)  <+ ddt(V(res,feed)*C);


end  //analog end
endmodule



Thanks

Peter Sjöblom
peter.sjoblom@es.lth.se