Hi all,

I would like to simulate a mixed-signal circuit using the mixed-mode capabilites of AMSDesigner.

The analog block has a 3.3V supply whereas the digital block has a 1.8-V supply.
In order to make them comminicate each other, some analog level-shifter are inserted between the analog and the digital blocks: there is the "A2D_shifter" to convert the 3.3V level into 1.8V level and the "D2A_shifter" (converting the digital signal from 1.8-V to 3.3-V).

For a single supply circuit I usually define a ConnectRule in the HierachyEditor->AMS->Simulation panel.
As far as I know, for a dual supply circuit I have to define two different ConnectRules: in fact the 3.3-V analog signal coming from the A2D_shifter has to be considered as "1"; on the other hand, the "1" level coming from the digital circuit has to considered equal to 1.8-V at the input of the D2A_shifter.

How can I define to different Connection Rules and how can I define in which part of the circuit those rules has to be used?
Does anybody ever meet this problem?  
I am not sure to be clear enough but I am ready to explain you more.

Many thanks in advance,
Cri

Its actually possible - using "supplySensitive" connect elements - to use a single logic discipline in the simulations..
But this always makes me nervous because it doesn't fail to simulate when you connect a 3v logic net to a 1v logic net.. (since there is only 1 discipline)
Easiest way is simply to create 2 logic disciplines..
since High voltage logic CAN be used at  lower voltage, I like to use a supplySensitive discipline for any 3v gates.. (ie logic_ss) and while I'd like to do the same for my 1v devices, I'd ahve to go back in all the verilog code from the StdCell Libraries and modify them to get the supply sensitive references in there.. Which I might do SOMEDAY, but for now, I just the default discipline..
Which I set to logic_cmos - because I know that "logic" is a keyword in systemverilog that is not related to disciplines.. so I refuse to use it anymore!

In my connect rules I don't allow a direct connection between logic_ss and logic_cmos.. But I can write my Shifters so that HV to LV has logic_ss input , logic_cmos output,
and the LV2HVshifter has logic_cmos input and logic_ss output.

I'll probably have to upgrade my stdcell libraries on my next project..
Cadence could probably send you a set of connect models like this if you don't have them..
- oh, you do have to
Code:

`include "disciplines_ss.vams" 

in each of the models where you use these disciplines
(you can put the path to these in your hdl.var file that is used when you netlist schematics.. and run ams)
so there is never a problem..
then you write the connectRules to include all of these,
L2E , E2L and BiDir for the logic_cmos to/from electrical
L2E_ss E2L_ss and BiDir_ss for the logic_ss to/from electrical
and you're set.