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jcpu2006

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Hsinchu

cdl out problem
Jul 03^rd, 2006, 7:08pm

Dear Sir:

when I use CDL out to export netlist from composor to HSPICE...
there is a line of "*.PININFO..." like:

.SUBCKT sc_res_P2_2d34P A1 A3 CK<1> CK<2> CK<3> CK<4> CK<5> CK<6> CK<7> CK<8>
+VAG VDD VSS
*.PININFO A1:B A3:B CK<1>:B CK<2>:B CK<3>:B CK<4>:B CK<5>:B CK<6>:B CK<7>:B
+CK<8>:B VAG:B VDD:B VSS:B
MM0 net054 net25 net054 VDD PD W=10u L=10u M=4
MM1 net054 net25 net054 VDD PD W=6.8u L=10u M=1
XI169 A1 net054 CK<7> CK<8> VDD VSS / switch_A
XI159 net25 A3 CK<3> CK<4> VDD VSS / switch_A
XI0 net054 VAG CK<5> CK<6> VDD VSS / switch_A
XI1 net25 VAG CK<1> CK<2> VDD VSS / switch_A
.ENDS

where most of other simulator shall take line "+CK<8>:B VAG:B VDD:B VSS:B" as comtinuation of .SUBCKT definition and syntax error occurs.
Please advise how to avoid this.
Thanks in advance!

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jcpu2006

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Posts: 19
Hsinchu

Re: cdl out problem
Reply #1 - Jul 3^rd, 2006, 7:50pm

Dear Sir:

Allow me to add another problem with CDL out:
When we define subcircuit parameter as pPar("LP")...
say in an invertor circuit. It's good for design and simualtion.
But when later we need to export its netlist for LVS or HSPICE postsim.
Netlist obtain from CDL out is:
************************************************************************
* Library Name: logic
* Cell Name: inv
* View Name: schematic
************************************************************************
.SUBCKT inv A VDD VSS Y
*.PININFO A:I Y:O VDD:B VSS:B
MN0 Y A VSS VSS N W=WN L=LN M=M
MP1 Y A VDD VDD P W=WP L=LP M=M
.ENDS
************************************************************************
===>
which is short of something like "WN=1u LN=0.5u WP=1u LP=0.5u M=1"
in the tail of first line to match the calling sequence

************************************************************************
.SUBCKT LNA_v2 ENA IN NBIAS OUT VDD VSS
*.PININFO ENA:B IN:B NBIAS:B OUT:B VDD:B VSS:B
XI7 ENA VDD VSS ENAB / inv LP=0.7u WP=2.6u M=1 LN=0.7u WN=1.3u
RR5 OUT VSS 3K $[RP]
RR3 net077 VSS 3K $[RP]
MM14 NBIAS net081 VSS VSS N W=10u L=4u M=1
MM3 net081 ENAB VSS VSS N W=2u L=2u M=1
.ENDS
************************************************************************

Please advise! Undecided

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Andrew Beckett

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Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK

Re: cdl out problem
Reply #2 - Jul 24^th, 2006, 1:54pm

I think for your first question, you probably need to put:

Code:

hnlMaxLineLength=1024

in your .simrc file (either in your current dir or home dir). I've not tested this - but it's probably something like that.

For the second question, this is perfectly legal CDL syntax - the parameters are defined on the calling instance, rather than having default values defined in the subckt itself.

If you want a HSPICE netlist, use an HSPICE netlister. CDL is a distinct (but similar) language to HSPICE.

Regards,

Andrew.

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jbdavid

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Posts: 378
Silicon Valley

Re: cdl out problem
Reply #3 - Aug 3^rd, 2006, 3:35am

Andrew Beckett wrote on Jul 24^th, 2006, 1:54pm:

If you want a HSPICE netlist, use an HSPICE netlister. CDL is a distinct (but similar) language to HSPICE.

CDL "WAS" an attempt to preserve "simulateability" with Physical Verification tools.. so that you could get some simulation infor from the cdl netlist, AND pass it to Dracula for LVS..

I do not think a modern PV flow should depend on implict port connections..
(keeping the same pin order in the subcircuit call as in the subcircuit definition.. )
this makes CAD guys waste MUCHO hours setting up CDF parameters so subcircuit calls get made with exactly the right order.. when a connection by name would be so much more robust.

Now perhaps VerilogAMS is not perfect, but Its a STANDARDIZED language, allows explicit connects AND parametere passing, so It much rather trust a successful LVS as being true to the intended connections, than with CDL..

Maybe I need a "NO CDL" graphic?

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jbdavid
Mixed Signal Design Verification

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