Dear Sir:
Allow me to add another problem with CDL out:
When we define subcircuit parameter as pPar("LP")...
say in an invertor circuit. It's good for design and simualtion.
But when later we need to export its netlist for LVS or HSPICE postsim.
Netlist obtain from CDL out is:
************************************************************************
* Library Name: logic
* Cell Name: inv
* View Name: schematic
************************************************************************
.SUBCKT inv A VDD VSS Y
*.PININFO A:I Y:O VDD:B VSS:B
MN0 Y A VSS VSS N W=WN L=LN M=M
MP1 Y A VDD VDD P W=WP L=LP M=M
.ENDS
************************************************************************
===>
which is short of something like "WN=1u LN=0.5u WP=1u LP=0.5u M=1"
in the tail of first line to match the calling sequence
************************************************************************
.SUBCKT LNA_v2 ENA IN NBIAS OUT VDD VSS
*.PININFO ENA:B IN:B NBIAS:B OUT:B VDD:B VSS:B
XI7 ENA VDD VSS ENAB / inv LP=0.7u WP=2.6u M=1 LN=0.7u WN=1.3u
RR5 OUT VSS 3K $[RP]
RR3 net077 VSS 3K $[RP]
MM14 NBIAS net081 VSS VSS N W=10u L=4u M=1
MM3 net081 ENAB VSS VSS N W=2u L=2u M=1
.ENDS
************************************************************************
Please advise!