Hi all,
We are now designing a pll base video demodulator. About the simulator in cadence, there are a few questions to need your help.
1) How to setup the input SNR that is to say how to add the white noise and phase noise into the source?
2) How to simulate the pll loop (Attention: phase loop) W3dB (3dB bandwidth) and Bn (noise bandwidth)?
3) What is the relationship between the input signal bandwidth and the loop bandwidth?

I appreciate well your help in advance.

Regards,
cybq