mkaragou wrote on Jul 12th, 2006, 4:02am:Ok, lets say I would like to perform a full blown transistor level simulation only, because I am to lazy to create a behavioral model.
And now I want to optimize the the loop filter paramaters to achieve fast phase lock and to ensure stability.
What is the optimum simulation strategy?
If you have some reasonable gauge of its stability, perhaps a transient simulation to obtain its phase step response might be a means of assessing its stability. Specifically, if you apply an input frequency with a phase step at some time and examine the resulting output phase (by post processing the output freqeuncy response), you can determine how closely ots response is to your expectation. Excessive output phase ringing or overshoot are certainly signs of less phase margin while an excessively slow damped response may indicate excessive damping.
I suppose an advantage of this method is that you are not relying on a behavioral model and any "hidden" subtleties in the specific implementation not captured in the behavioral model. I would also recommend using various phase step sizes as the phase step response may be a string function of the input phase step amplitude. If, for example, your loop has a frequency acquisition aid, its response will differ significantly if the frequency acquisiton aid is invoked.
Just a few thoughts anyway...