Hi,
I am designing a highspeed opamp for a pipelined ADC application. The required UGB is anywhere between 800Meg to 1G. The design is on 0.35u process. I have chosen folded cascode with gain boosting technique for the amp (A fully differential opamp with SC-CMFB). To meet the high gain spec , I have no other option than to pump more and more current into the opamp. This made my transistors too big. Though the schematic is working fine, I encounter problems when I simulate C-extracted version. The parasitic caps due to huge transistors prove fatal to my phase margin and speed. Now my question is

1)Before proceeding into high speed design, are there any subtle points I need to take care of?
2) Is there anyway I can bypass these huge sizes of transistors?

Any reference or book on this issue will be highly useful.

Thanks
kalluru

Do you really want an op-amp here?

The stated bandwidth was up to 1GHz. Typically I stop using feedback amplifiers above 100MHz or so (for 0.18 CMOS types of processes)

Consider some common source differential pair amplifiers, without feedback. and you will need to do some correction circutis for gain errors, watch your linearity, and things like that.