I am trying to simulate a self biased PLL in Cadence spectreRF. It runs fine (locks) in the schematic with initial conditions on the output nets of the VCO. I need to know if that is how a PLL is simulated (transient simulation). I heard that PLL is to be simulated without any initial condition and using a start up circuit. If I don't use any start up circuit or initial condition the PLL doesn't work properly.
I will appreciate if anybody could answer my querries.
Thanks.