smlogan
Community Member
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Posts: 52
Boston, MA
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Hi Sachin,
I just designed a duty cycle correction circuit after studying a previous version that was not adequate. A couple of items come to mind...
1. The range of duty cycle correction you must consider and a low jitter solution require a compromise. The larger duty cycle range that you must cover suggest a higher sensitivity to jitter. I'm not sure of the A/D topologyyou are considering. However, the fact that it requires a 50+/- 1% duty cycle suggests that jitter on both edges of the clock is important. The solution I adopted, over silicon process and environmental effects was able to correct between 30% and 70% duty cycles to within 1%.
2. If at all possible, I would suggest examining the impact of distributing a clock to the A/D at twice its current frequency. By dividing the clock locally, if a duty cycle correction circuit is still necessay, you might only have to correct for a 1 or 2% duty cycle error. This will allow a much less jitter sensitive solution. Of course, if the flip flop propagation delay is low enough relative to the clock frequency, a duty cycle correction circuit may not be necessary.
Let me know if you have any idea as to the magnitude of phase jitter requirement on the A/D clock.
Shawn
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