Hi Sachin,
I've never designed one of these, never even heard of one, but I think something like this should work:



If you're clocking an ADC with the output of your circuit, then you probablly only care about jitter on one edge (rising or falling).  In this circuit, that edge would be generated by the lower path.  There are no delay elements in this path, so jitter will be low.

-Dan

Hmm... not qite sure why I put two FFs in there.  This is better:

-Dan

Hi Sachin,

I just designed a duty cycle correction circuit after studying a previous version that was not adequate. A couple of items come to mind...

1. The range of duty cycle correction you must consider and a low jitter solution require a compromise. The larger duty cycle range that you must cover suggest a higher sensitivity to jitter. I'm not sure of the A/D topologyyou are considering. However, the fact that it requires a 50+/- 1% duty cycle suggests that jitter on both edges of the clock is important. The solution I adopted, over silicon process and environmental effects was able to correct between 30% and 70% duty cycles to within 1%.

2. If at all possible, I would suggest examining the impact of distributing a clock to the A/D at twice its current frequency. By dividing the clock locally, if a duty cycle correction circuit is still necessay, you might only have to correct for a 1 or 2% duty cycle error. This will allow a much less jitter sensitive solution. Of course, if the flip flop propagation delay is low enough relative to the clock frequency, a duty cycle correction circuit may not be necessary.

Let me know if you have any idea as to the magnitude of phase jitter requirement on the A/D clock.

Shawn

The most efficient way of getting this done sort of ducks the question.

Distribute a 2F clock, and locally divide it down by 2.

In RF mixers this is how they get best quality mixer LO symmetry.

Other methods include heavily filtering the signal (get it down to the fundamental sinusoid) and then run it through an AC coupled amplifier and get back up to the square wave.

PLL and DLL methods work well also.

Those are the methods that come to mind quickly.

hope that helps,
Jerry

Hi Cirand,

I'm curious what you used for pulse generator in your duty cycle correction circuit as described in the attached paper.

Thanks,
ccd

Thomas Lee had a paper on JSSCC on this, you can check with that.
It is published in 2002, or 2000.

ywguo wrote on Oct 19^th, 2006, 7:32pm:

hi Yawei,

the method proposed by the paper is too complex, i think there are three very simple ckt techniques you can find.
one is proposed by j.maneatis.
the sencond one given by LEE and KIM: "low-noise fast-lock Phase-locked loop" a jssc paper.
the third one given by a.maxim in his paper "A Low-Jitter 125 ~ 1250 MHz Process Independent and Ripple Poleless 0.18μm CMOS PLL Based on a Sample-Reset Loop Filter".
good luck
jeff