Andrew Beckett
Senior Fellow
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Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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You can use File->Import->CDL to read in a CDL netlist and generate a schematic. You can provide a device mapping file to map it to your design kit.
Having done that, you can create a symbol from the schematic (as you would a normal schematic), and then you can simulate it via the normal ADE flow.
Alternatively, since CDL is essentially SPICE, you could create a symbol (in a schematic, use Design->Create CellView->From Pin List and type in the pin names). Then in the CDF for the component, specify the termOrder for spectre to match the terminal order in the netlist. And then in ADE specify the CDL file as a model file.
The above are both rather abbreviated descriptions of what you need to do, but it's quite straightforward really. I just don't have time to do a detailed step-by-step description at the moment (especially as I'm typing this without access to the Cadence software).
Regards,
Andrew.
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