dragonzj
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As we know that the pll synthesizer has some main directive:the phase noise,the reference spurs,non harmonic spurs,the step size,reference phase noise,settling time....these directives affect each other.So when we optimize one,the other is deteriorated,for example,when we decrease the loop bandwidth,we can achieve good spur suppression,but it lead to the increase of the phase noise.So I hope that some one can give me more example of such cases so that I can sum them up.I think they would be very helpful when we designing our synthesizers.
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