I am implementing a decision feedback equalizer in CMOS. For high speed implmentation most DFE topologies I have found use clocked decision and delay blocks (digital) and the ISI cancellation is done in current mode (analog) at the input of the decision slicer. So it is a mixed signal approach. The DFE forms a negative feedback loop as the data decision signals control NMOS current switches that make the correction at the input of the decision slicer. I am interested to know if any sort of conventional ac stability analysis is required for such a topology. None of the papers I have looked at go into the conventional phase margin type of stability analysis. Is that because the circuit is not operating in the small signal regime? The clocked slicer and delay blocks will be high gain. So employing a high gain path in a feedback loop brings up stability issues and maintaining a  closed loop phase margin less than 180 degrees is not feasible. However, transient simulations show good results and no signs of unstable behaviour ( undamped oscillations). What sort of stability analysis is required for a mixed signal DFE topology? Any thoughts or comments on this subject will be appreciated.

Thanks Jerry. This confirmed what I had been thinking as well. I am looking at DFEs as part of my PhD research. DFEs are being looked at now to comabt ISI in multigigabit wired channels (backplanes, optical fiber). They were originally used in disk drives and now mixed signal topologies are being used to for high speed channel equalization. I can send you soem papers if you are interested.

Thanks, again

Soumya