Hello all,

I am new to verilog-A and I am building some behavioral model for a delta sigma modulator. I did the same thing using simulink before but this time I would like to try using verilog-A instead. Unfortunately, things does not go as what I think it would and I run some test case using some basic sample and hold. This is what written in the verilog-A reference that will implement an ideal sample and hold.

V(vo) <+ zi_nd(V(vi),{1},{1},period,trans);

There are something about the parameter "trans" in the function. At first, I thought it would be good to model the finite slew rate of most circuit have, so i just set it 1ns. When I cascade 2 SH together, I was expecting to see the output of them to be the same since there is no delay in the transfer function, but I found that the output of the second SH is actually being delayed by 1 period. I did the same thing using simulink and confirm that the output should be the same in this case.

Apparently when I specified the transition time, the second SH sample the data from the first SH before the output fully transition to the correct output, causing it to delay by 1 period and I guess that is why my verilog modulator is not stable in the first place because of the extra delay. Is anyone having the same problem? Can anyone confirm that?

chase