smlogan
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Boston, MA
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Hi Vivek,
Another thought thay may (or may not!!) be useful to consider. I have been faced with a similar design situtation a number of times in the distribution of a reference clock to a SerDes. From measurements I've taken and the level of phase jitter I've been faced with meeting, the two dominant sources of signal integrity presented by the additional buffering are added deterministic jitter from the buffers (due to supply/ground noise) and the potential for differential skew. I'm not sure if your application uses a differential clock - hence the latter consideration may not be important to you.
For the case of added power supply or ground noise, many designers analyze this by modulating the supply or ground with either a single sinusoidal source or a broadband noise source and examine the resulting output phase jitter of the buffer. This can be accomplished through a series of transient simulations or harmonic balances simulations followed by a a noise analysis based on the harmonic balance solution.
However, a less computationally rigorous technique is to study the propagation delay through the buffer(s) of interest - from even a DC perspective. By examining the variation in the propagation delay of the buffer(s) as the supply voltage is changed, a direct measure of its variation with supplyvoltage is obtained. The resulting variation in prooagation delay will translate to phase jitter over the frequency range where the buffer can translate VDD-VSS variation to propagation delay - which is usually quite high in frequency. This can provide a direct indication of how sensitive the output jitter of a buffer - or series of buffers - is to noise on the supply or ground.
This technique can also be used to examine the amount of differential skew that will be imposed on a differential signal. Specifically if the variation in tpd (high->low) is different than the variation in tpd (low->high), then the skew will be a function of the amount of supply/ground modulation.
If this is not appealing to you, a series of transient simulations of the buffer(s) with different amaounts of differential input skew can be used to establish the robustness of the buffer(s) to the presence of differential input skew. As some differential buffers are designed to reduce input differential skew, this technque provides a direct indication of the degree to which differential input skew is attenuated.
I hope this is of some help!
Shawn
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