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voltage vs. electrical (Read 7800 times)
Aigneryu
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voltage vs. electrical
Aug 09th, 2006, 12:59pm
 
Hi,

 Recently I am converting all my previous macro-models from vlog-a to vlog-ams, and
also migrate from spectre-vlog to AMS. I found that some terminal with "voltage" discipline
can be used in spectre/spectre-vlog simulation, but I have to to change to "electrical"
discipline if I want to use them in AMS simulator.

So why these disciplines make such difference between old mixed-mode simulator and
AMS designer? since I am pretty sure that no current will flow in to/out from
the terminals.


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Ken Kundert
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Re:  voltage vs. electrical
Reply #1 - Aug 9th, 2006, 10:35pm
 
If you do not need to access the current, then you should be able to use "voltage" rather than "electrical". This might be a limitation in AMS Designer.

Perhaps you can post your model so we can take a closer look.

-Ken
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Daniel_Platte
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Re:  voltage vs. electrical
Reply #2 - Aug 9th, 2006, 11:39pm
 
Hi NG!

I have had a related problem:

Does Spectre support voltage as a signal-flow quantity? I was using it for modeling expecting that it would reduce the dimension of the system. As I can see from the logfile of Spectre, the number of equations is not reduced by changing from electrical to voltage.

Does anyone have an explanation for this? What is the benefit of using the signal-flow quantity (instead of electrical) then?

Cheers
Daniel
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Aigneryu
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Re:  voltage vs. electrical
Reply #3 - Aug 10th, 2006, 1:53pm
 
This netlist is built with Ken's vco vlogams netlist in this forum.
I just simply connect a vdc (taken from analogLib) to connect to the input of vco, and set to 1V and the negative end is connect to the gnd!
It fails when I try to simulate
BUt if I change the disciplin from voltage to electrical, it will work.

There is second part of the netlist given in the next post.


//
// Design File for: (VFS_AMS_PHY180_sims test_vco schematic)
//
// Verilog-AMS netlist generated by the AMS netlister, version 5.10.41.500.2.25.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
`include "userDisciplines.vams"

module test_vco (  );





vco_j (*
integer library_binding = "VFS_AMS_PHY180_sims";
*)
I10 ( .in(
vctrl ), .out( vosc ) );

vsource #(.type("dc"), .dc(1)) (*
integer library_binding
= "analogLib";
*)
V0 ( vctrl, cds_globals.\gnd!  );

endmodule

//
// Design File for: (VFS_AMS_PHY180_sims vco_j verilogams)
//
//Verilog-AMS HDL for "VFS_AMS_PHY180_sims", "vco_j" "verilogams"



`include "disciplines.vams"
`include "constants.vams"

//
// Voltage controlled oscillator with no jitter
//

module vco_j (out, in);

input in;  voltage in;                        // input terminal
output out; voltage out;                  // output terminal
parameter real vmin=0;                        // input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf);      // input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf);            // minimum output frequency
parameter real fmax=2*fmin from (fmin:inf);      // maximum output frequency
parameter real vl=-1;                        // high output voltage
parameter real vh=1;                        // low output voltage
parameter real tt=0.01/fmax from (0:inf);      // output transition time
parameter real ttol=1u/fmax from (0:1/fmax);      // time tolerance
real freq, phase;
integer n;

analog begin
   // compute the freq from the input voltage
   freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

   // bound the frequency (this is optional)
   if (freq > fmax) freq = fmax;
   if (freq < fmin) freq = fmin;

   // phase is the integral of the freq modulo 2p
   phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

   // identify the point where switching occurs
   @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol))
     n = (phase >= -`M_PI/2) && (phase < `M_PI/2);

   // generate the output
   V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule
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Aigneryu
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Re:  voltage vs. electrical
Reply #4 - Aug 10th, 2006, 1:54pm
 
//
// Design File for: (VFS_AMS_PHY180_sims cds_globals test_vco_config)
//
// Verilog-AMS cds_globals module for top-level cell:
//    VFS_AMS_PHY180_sims/test_vco.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
  electrical \gnd! ;
  ground \gnd! ;

// Design Variables

endmodule

// This is the Cadence AMS Designer(R) analog simulation control file.
// It specifies the options and analyses for the Spectre and UltraSim
// analog solvers. To facilitate using the file outside of
// Cadence environments, the file includes options for both solvers.

// Many options between Spectre and UltraSim share similar
// names or semantics but the values used are different
// depending on solver. For this reason, these particular
// options are solver specific.


simulator lang=spectre


// The following options are used by both analog solvers.

commonOptions1 options temp=27
commonOptions2 options tnom=27
commonOptions3 options scale=1.0
commonOptions4 options scalem=1.0


// The following options are used by only the Spectre solver.
// The UltraSim solver ignores these options.

*--------------------------------------------------------*
* Spectre Solver Options
*--------------------------------------------------------*
spectreOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 gmin=1e-12
+   rforce=1 maxnotes=5 maxwarns=5 digits=5 pivrel=1e-3


// The following options are used only by the UltraSim solver.
// The Spectre solver sees the "*ultrasim: " prefix and
// ignores these options.

*--------------------------------------------------------*
* UltraSim Solver Options
*--------------------------------------------------------*
*ultrasim: .usim_opt output_upper=0 ade=1 wf_spectre_syntax=1

// The following option statements specify the Transient analysis.
// Some of the parameters are used by both solvers. The subset
// noted below explains what is supported by each solver.

tran tran stop=10u save=none write="spectre.ic" writefinal="spectre.fc"
//  The following parameters are used only by the Spectre solver.
//  They are present in the SPECTRE TRANSIENT PARAMETERS section
//  of ADE transient analysis GUI. The UltraSim solver ignores
//  these parameters.
+   maxiters=5 annotate=status

// The following info statement, which is used by both solvers,
// returns the final operating point from the last timepoint in the
// transient analysis. Writing out the operating point can result in a
// large operating point results file, especially when using UltraSim on
// large designs.  For this reason you can enable/disable this analysis
// for the UltraSim solver by using the 'Save Final Op Pt' option,
// in the ULTRASIM TRANSIENT PARAMETERS section of ADE transient
// analysis GUI.

finalTimeOP info what=oppoint where=rawfile

// The following statements, which are used by both solvers, save
// internal simulation data. These "analyses" can be turned
// OFF from the ADE save options GUI.

modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile

# This is the NC-SIM(R) probe command file
# used in the AMS-ADE integration.


#
# Database settings
#
database -open ams_database -into ../psf -default

#
# Probe settings
#
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Aigneryu
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Re:  voltage vs. electrical
Reply #5 - Aug 10th, 2006, 1:59pm
 
The error message is:

ncelab: *E,CUVDNF (./ihnl/VFS_AMS_PHY180_sims/test_vco/schematic/verilog.vams,17|4): Could not determine discipline for this expression .
V0 ( vctrl, cds_globals.\gnd!  );
        |
ncelab: *E,CUVDNF (./ihnl/VFS_AMS_PHY180_sims/test_vco/schematic/verilog.vams,23|9): Could not determine discipline for this expression .
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