Aigneryu
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This netlist is built with Ken's vco vlogams netlist in this forum. I just simply connect a vdc (taken from analogLib) to connect to the input of vco, and set to 1V and the negative end is connect to the gnd! It fails when I try to simulate BUt if I change the disciplin from voltage to electrical, it will work.
There is second part of the netlist given in the next post.
// // Design File for: (VFS_AMS_PHY180_sims test_vco schematic) // // Verilog-AMS netlist generated by the AMS netlister, version 5.10.41.500.2.25. // Cadence Design Systems, Inc.
`include "disciplines.vams" `include "userDisciplines.vams" module test_vco ( );
vco_j (* integer library_binding = "VFS_AMS_PHY180_sims"; *) I10 ( .in( vctrl ), .out( vosc ) ); vsource #(.type("dc"), .dc(1)) (* integer library_binding = "analogLib"; *) V0 ( vctrl, cds_globals.\gnd! );
endmodule
// // Design File for: (VFS_AMS_PHY180_sims vco_j verilogams) // //Verilog-AMS HDL for "VFS_AMS_PHY180_sims", "vco_j" "verilogams"
`include "disciplines.vams" `include "constants.vams"
// // Voltage controlled oscillator with no jitter //
module vco_j (out, in);
input in; voltage in; // input terminal output out; voltage out; // output terminal parameter real vmin=0; // input voltage that corresponds to minimum output frequency parameter real vmax=vmin+1 from (vmin:inf); // input voltage that corresponds to maximum output frequency parameter real fmin=1 from (0:inf); // minimum output frequency parameter real fmax=2*fmin from (fmin:inf); // maximum output frequency parameter real vl=-1; // high output voltage parameter real vh=1; // low output voltage parameter real tt=0.01/fmax from (0:inf); // output transition time parameter real ttol=1u/fmax from (0:1/fmax); // time tolerance real freq, phase; integer n;
analog begin // compute the freq from the input voltage freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;
// bound the frequency (this is optional) if (freq > fmax) freq = fmax; if (freq < fmin) freq = fmin;
// phase is the integral of the freq modulo 2p phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);
// identify the point where switching occurs @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol)) n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
// generate the output V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule
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