I recently upgraded cadence and since the update I keep running into simulation problems with spectre when simulating VerilogA files. The spectre version in use is 5.1.0 10/24/2005. The problem is the following: When changing already existing verilogA code that I had run previously Spectre gives me a segmentation fault. I noticed that when I delete the created compilation directory filename.va.ahdlcmi and re-run it then it works fine. This did not used to be like this. Before the update I could change the VerilogA code and never run into a segmentation fault. Any ideas why that is? BTW, I am using RedHat EL4.

Regards,
Sven

The PCR is:

   PCR: 850785
 Title: bus error when modify veriloga code and rerun simulation

The problem was partly fixed in IC5141 USR3, but that's the version you're using.

I think you need to do a Simulation->Stop before modifying the Verilog-A code - and then it should
be OK. The bug still hasn't been fixed - we need to trigger a stop and restart of spectre to
cure this.

Regards,

Andrew.

yee, i also used to get this darn error frequently. it used to pop up after some three four simulations if done one after another.

what i usually do is copy that same code to another cell view. then it'll start running properly.