Designer’s Guide Community

raftman

Junior Member

Offline

Posts: 11

Spectre and SpectreVerilog discrepancy
Aug 10^th, 2006, 3:35pm

I am seeing a significant discrepancy between the Spectre and SpectreVerilog simulators. The circuit in question is a bootstrapping circuit - and what I'd like to do is track down exactly which models each simulator is using.

I'm familiar with the switch/stop viewlists, but I think the issue might be in the model structure. Instead of an .scs file for each device in the kit, the model files are setup as process corners and have different sections (fast, typ, slow, etc). Then while simulating I have to go to 'setup corners' or 'corners' from the Analog Environment window and select typical for actives, resistance, capacitance, etc. So If I select fast for poly, the simulator apparently generates the correct model for each MOS device.

I have also setup AMS and the results here match with SpectreVerilog.

So, if I can get some help tracking down exactly what model is being used for MOS devices in each case I'd be most appreciative!

Thanks!

Back to top

IP Logged

jbdavid

Community Fellow

Offline

Posts: 378
Silicon Valley

Re: Spectre and SpectreVerilog discrepancy
Reply #1 - Aug 11^th, 2006, 1:04am

Hopefully what you have in the SpectreVerilog and AMS simulation is a combination of GATE level behavioral models with analog circuits..
The analog circuit behavior is probably no different.. and uses the same models in any of these simulations.
but frequently the logic models assume that supplies are ALWAYS ON.. so the logic will work even if the voltage is NOT really there..
Also your interface elements or connect models may not be setup to use the actual supply voltage for the logic levels..

In short - ALL are using the same device level models for MOS devices..
But the mixed signal sims are using gate level models for some blocks.. and those
run in the LOGIC simulator with outputs that are either 0,1 Z or X.

This is why you are getting the same results with both mixed signal simulators..

Back to top

jbdavid
Mixed Signal Design Verification

IP Logged

raftman

Junior Member

Offline

Posts: 11

Re: Spectre and SpectreVerilog discrepancy
Reply #2 - Aug 11^th, 2006, 6:34am

Thanks for your input. While what you're saying makes sense - I have to think that the analog components are behaving differently (be it from models or some other cause) because my testbenches are as follows:

Spectre - Just the analog bootstrapping circuit

SpectreVerilog/AMS - same analog bootstrapping circuit (with same inputs) and a dummy functional verilog block whose signals drive an nMOS device and whose signals do not interact with the analog circuit.

Both are running 'conservative' mode transient sims. However, maybe I should recheck the tolerance values.

-Raftman

Back to top

IP Logged

jbdavid

Community Fellow

Offline

Posts: 378
Silicon Valley

Re: Spectre and SpectreVerilog discrepancy
Reply #3 - Aug 12^th, 2006, 2:37am

I don't recall a "corner" selection form in the Spectre simulator environment..
usually the MODELS form will list the files, and section from each .. ie for tsmc13
I see
rf013.scs tt
rf013.scs tt_lvt
cl013g_res.scs res_tt

where the model path has been set in the simulation Files window..

just cd to the directory and "more" the rf013.scs file, look for "Section"
but what you are describing sounds more like SpectreSverilog.. or SpectreS..
which I haven't used since 2000..
Jonathan
Jonathan

Back to top

jbdavid
Mixed Signal Design Verification

IP Logged

raftman

Junior Member

Offline

Posts: 11

Re: Spectre and SpectreVerilog discrepancy
Reply #4 - Aug 25^th, 2006, 8:32am

what i am referring to is under tools -> corners in the analog environment window. I cannot just go to simulation -> netlist and run since no model path is provided in the setup -> simulation files window. However, if I go to tools -> setup corners, I can generate a single model file based on which process corner sections I choose. After this file is generated and saved I can go to simulation -> netlist and run, and simulate succesfully.

That is all running the spectre simulator.

However, when using spectreVerilog I am not able to use tools -> setup corners, but rather instead have been simulating through the tools -> corners interface.

Thanks.

Back to top

IP Logged

jbdavid

Community Fellow

Offline

Posts: 378
Silicon Valley

Re: Spectre and SpectreVerilog discrepancy
Reply #5 - Aug 30^th, 2006, 1:00am

Ah.. the Corners tool..
I thought you were talking about the NORMAL simulation environment...
you should not use the Corners tool until you can run a normal simulation..
(I don't even have license for that environment..)
But I have set it up before.. (it actually had a stupid problem with using more than one section from the same model file when It was first released which meant that setting it up for TSMC required making up separate model files for each set of the sections you wanted to call
which then called the REAL model file.. (which I don't touch (except for Subversion version tags..) )

but again, you are LIKELY (I can't be sure with out looking at your environment - and I'm not a consultant yet.. )
on the wrong trail.. They should ALL be using the same models..
its the Verilog , and interface elements that should be making all the difference..

to be sure though the EASIEST thing to do is setup so you can run the simulations WITHOUT using the corners simulation gui..
(it did less that Aptivia does - and THAT still had significant issues.. at least for MY careabouts)

then make sure the connect modules are correct.. ( you did change the voltage from 5v to your own case right??)

etc.. I can't help you with that corners tool thing .. easiest to get it out of the picture..
jbd

Back to top

jbdavid
Mixed Signal Design Verification

IP Logged