Hi Arun,

In schematic simulation, it is rare to specify metal wiring capaciatnce or resistance unless the designer knows it to be critical or one is considering RF design.
So long as your kit is installed correctly (ie your techfile has the thick M6 layer available and you have the right verification decks) you can do layout-backextraction using Assura (or diva etc.) and you get the parasitic R or C associated with a layout design... this will include thick M6 (again assuming the foundry has setup the Deck ok).... I have used UMC before, and I recall although they aren't great (like IBM) when it comes to PDK, they're ok...

If you are designing inductors or similar, then you will need to use a specific design tool (fastHenry, ASITIC, Momentum, Sonnet etc.) which extracts inductance and lossy parasitic C, in which cases you need to input the process cross-sections (dimensions, material er or pho/sigma etc.) yourself. If you are using the Cadence tool, you can enter these details in the form under ADE->Tools->RF->...
Personally i use ASITIC for modeling of Inductors, transmission lines, RF coupling etc.

Cheers

aw