I've been doing some reading on the subject and found very limited info. I thought I throw this out there to learn something from you ESD guru in the forum.

In a multi-power segments IO ring, ESD conducting module (back to back diode) are used to separate each power segment. Given a scenario where each segment can be power down and the process is a sub-micro process with very high leakage, the task of balancing the leakage (increasing the # of back to back diodes) and ESD performance (wanting to keep the diode chain to minimum) become quite difficult.  Can some of you ESD guru comment on how you would approach this problem and what would be your strategy on this balancing act?

I also searched for paper on the subject and only come across one paper discussing the issue ESD performance vs the #'s of power segments?  Does anyone has a rule of thumb of how many power segments can a chip has before killing the ESD performance?

Also, consider not breaking the grounds apart.
Sometimes (not all the time!) it is not worth it.

At the end of the day when you have things split, and ESD B2B diodes in place and all that (amps of current need to go thru!) the "seperated grounds" are dead short connected due to all the capacitance between them.

Do a quick and dirty AC spice analysis and you will see what I mean.

Jerry

ACWWong: what is highest # of domains have you built in a single chip? >5? >10? What is the best way to determine the upper limit of this number?

Loose-e: true, sometime breaking the ground is not necessary.  I have seen the b2b diode added for the ground for the purpose of noise isolation.  In theory, I can understand this but I have not come across a paper/publication that analyse the effectiveness of that.  How good is the isolation? How much better if the diode string is 2 diodes vs one?  Have you seen any published work in this area?

Most of the B2B diode stuff I have seen has been more "in the lab" than in a paper.
I don't believe every IEEE paper I read, they are not perfect.
(I can get away with taking that shot, I am a reviewer for both JSSC and MTT)

If you want to see how good the isolation is, start adding up all the parasitics between the two and do a quick analysis of that. At RF it is all shorted together. Then it becomes a question of "where RF starts" and that is open to debate.

Two ground domains sounds good to me. Going up to 6 sounds a little crazy IMHO.

Jerry

Three oscillators running on the chip.  Ouch!

How many noise problems did you have first time out?
I got pulled in to debug a chip like that once and the digital designer was clueless on noise issues, we ended up re-floorplanning the chip and a dozen other things to get it quiet and happy.

Jerry

I think we are going in circles a bit here.

If you can be a lot more specific about what you have perhaps we can be of help.

Jerry

I am going to take a shot at this thread and try not to repeat what anyone has already stated as there are many good reponses here.

My thoughts or "rule of thumb", take them with a grain of salt:

 There is no right # of domains or max # either, I have built padrings for large mixed-signal products that had upwards of 50 separate domains (don't ask..not my preference).

The trick is ensuring that everyone has an low impedance path for large ESD currents from any domain to any other domain.

It is best to avoid trying to tie all domains to each other using b2b diode, layout becomes a nightmare and it is not a good ESD approach.

Do not attempt to diode connect power supplies together, especially in a part with mixed voltages and different power down modes unless you are absolutely positve that you understand every potential user implementation your customers will dream up.

The solution to these SoC products is to pick the largest 'substrate' ground domain on the product and use that domian as the common ESD node.

All grounds must have b2b diode'S' to the large substrate ground.  (layout and placement is critical here).

All powers must have excellent clamping to their respective grounds.  if this is true than those respective grounds will pass ESD currents to the rest of the chip through their b2b diodes to the primary substrate ground and there will be no further need to clamp different power supplies to each other and complicate your power down modes.

This also helps with leakage as you will have no b2b diode with voltages on them, the only b2b will be between grounds where the voltage potential will likley be ~0v across the diode.

Regarding noise: I have seen many of loose-electrons comments on noise on these boards and I very much like his approach.  Few people really understand noise and many people have an unhealthly paranoia in trying to avoid it. Loose_electrons previous comment is correct..study the parasitics and do the analysis.


...Now please forgive me this very crude hand analysis example, but I feel it makes the point correctly.
If I have a b2b diode with 0.7pF of capacitance (this is a large conservative number mind you), it will ideally act as an 45 ohms impedance to a 5Ghz signal.  however if my ground impedance for my supplies on either side of the diode is say 2 ohms at 5Ghz (bond wire, metal resistance etc etc),  than any noise coupling across the diode is divided down between 45 ohms into 2 ohms (-27dB..of whatever noise is coupled), and this is at 5Ghz, its much lower as frequency lowers, I am not even taking into account the PSRR ratio of my individual blocks and so forth.  Now if you are desiging an LNA on an integrated baseband RF chip, 27 dB may not be enough, but for most applications, including analog PLL and oscillators it very well maybe.
Alot also depends on how much actual noise is generated on your noisy supplies. (25mV attentuated by 27dB is very different from 500mV attentuated by 27dB)
Basically, do the analysis before you panick about ESD noise coupling is what I am saying.


If your noise anlysis shows that you may be better off with grounds shorted together..do it!  Sometimes when you short multiple grounds together the overall noise actually lowers as the overall impedance for that larger ground domain is lowered; as it becomes larger and takes advantage or more pins/bondwire/decoupling, etc offchip.

On another note, do not muck around with trying to tailor the ESD connections for large inductive isolation.  Remeber that CDM ESD currents have enegy high into the GHz range, any inductive isolation will isolate those enegrgies as well and nullify your ESD structures.  It is a very bad practice to inductively isolate ESD structures if you want to pass CDM type events (which face it, are more reflective of todays manufacturing enviroment.)

I will stop here...

ACWong,
Thank you for the comment.  In light of your correction, I feel I should have better explained the background from where I was drawing my example.
 I used 2 ohms to represent the entire power domain (though I should have written 'bondwire' as plural 'bondwires', my mistake), as I have seen such impedances when I had domains with either many bondwires or flipchip with many bumps.  In many of the modern packages I also typically have bondires that are usually less than 0.5mm (~15 ohms@5Ghz per bondwire), especially in small MMAP, QFN, QFP or BGA packages.  I especially like QFN as all the grounds are down bonded thru real short wires to the die flag.
If I was trying to model a domain with a single bondwire, than yes, 2 ohms is way off base.

Either way 2 ohms may or may not be reasonable example for a situation, so it goes back to what we both have emphasized... do the analysis.

On a side note I will second your comment on good layout techniques.  That can not be stressed enough.  Designers would do well to heed your advice there.

Regards,
SRF