Designer’s Guide Community

‹ Previous topic | Next topic ›

Pages: 1 2

ESD strategy in a multi-power domains chip (Read 21566 times)

loose-electron

Senior Fellow

Offline

Best Design Tool =
Capable Designers

Posts: 1638
San Diego California

Re: ESD strategy in a multi-power domains chip
Reply #15 - Nov 13^th, 2006, 10:08am

ACW and SRF -

Good comments folks, I especially liked the concept of using the largest substrate ground as the common tie point.

One minor element to remeber on ESD - You need to have an ESD scenario that plugs and plays in both a packaged device, and a raw die (no package, no bond wires) as well.

Most, but not all, assembly houses have cleaned up their ESD problems in-house, but I ran into a chip a couple years back where the ESD was dependent on the interconnecto of the package, and a heap of chips were getting fried between wafer test and final package test.

Jerry

Jerry Twomey
www.effectiveelectrons.com
Read My Electronic Design Column Here
Contract IC-PCB-System Design - Analog, Mixed Signal, RF & Medical

IP Logged

SRF Tech

Community Member

Offline

Posts: 59
Arizona

Re: ESD strategy in a multi-power domains chip
Reply #16 - Nov 13^th, 2006, 2:32pm

Jerry,

The large common ground point has worked very well for me on many different products and technologies, but as ACW pointed out, layout and placement of the diodes and power bussing become critical with this approach. In all honesty, to do it right, you should also address noise and power distribution at the same time.

With regard to your point about raw die, that is an excellent reminder. I have seen more and more issues lately with problems related to this, and to a greater degree, in multi-chip packages where the ESD becomes dependent on the relationship between multiple die and their related interconnect in the same package.

regards,
SRF

Excellence in ESD and IO Design
www.srftechnologies.com

IP Logged

Pages: 1 2

‹ Previous topic | Next topic ›