Hi,

I have a digital design GDSII file. After importing to Virtuoso to generate a layout view as well as obtaining the schematic, I do a LVS check (DRC has passed before LVS). There are some property errors of transistor width errors on some standard library cells. For example, I open the cell schematic view, one transistor width is 1.53u in an AND gate cell. But on the layout view, the specified active region in the REV (green color in my Virtuoso setup) is 0.54u. I don't know how to check if the specified region is corresponding to the transistor on the schematic view.

I am completely new to the LVS procedure and wonder why this could happened. If layout depends on the standard library, then this discrepancy should not be occurring, right? More important, any suggestions on how to solve them?

Thanks in advance.