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aaron_do Senior Fellow Offline Posts: 1398	channel select filter Aug 22^nd, 2006, 8:26am Can anyone tell me what is the most popular method of tuning a bandpass channel select filter so that it doesn't vary over process. For example an automatic tuning loop. Currently designing for a 2 MHz IF and 1 MHz BW.
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ACWWong

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Re: channel select filter
Reply #1 - Aug 22^nd, 2006, 11:40am

make filter (or filter section) into an oscillator and count the the frequency and compare it to a known clock freq (from xtal) in 1 of two ways:

1) state machine which counts the filter oscillation and trims either C or R or gmC in a digital fashion to ensure centre freq is within a certain accuaracy.
2) continuous "master-slave" tuning, a kin to an analog pll that controls Idc in a gm cell.

I prefer 1 and have used it few times well. If your filter is bandpass and ladder, it will oscillate nicely if fedback on itself in "calibration mode". If you have cascaded biquads, you can create a copy of your highest Q section and make it into an ocsillator. Appropriate trimming of the gm or C will ensure you tune centre and bw in a tracked fashion. In cicrumstance where your Q is very high, some Q trimming may also be necessary.

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Re: channel select filter
Reply #2 - Aug 23^rd, 2006, 8:04am

what is your filter architecture? Op-amp and RC? Or a gmC structuree?

I have tuned the -6dB point using a clock that had been degenerated into a sinusoid, then resistive divide by 2 and compare the amplitudes, pre-post filter.

The PLL and gm stage method works (as ACW describes) works as well.

Tsividus (search IEEE JSSC) was a big fan of the MOSFET-C architectures, and adjusting the resistance of the FET.

lots of options...

Jerry

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aaron_do

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Re: channel select filter
Reply #3 - Aug 23^rd, 2006, 5:58pm

thanks guys,

i was thinking though that i could not include the automatic tuning as long as the filter maintains the required rejection of the adjacent and alternate channels over process variation. It seems to me that with a good current reference that the main variation will be in the capacitors, which vary about 10%. So if my filter is designed well enough it can deal with a 10% variation in the center frequency and still meet specs. What do you think?

Aaron

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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: channel select filter Reply #4 - Aug 23^rd, 2006, 6:30pm Which architecture - gm-C?, Op-amp with R, C? Mosfet-C? Sorry, not just the C... they all have process variance (R, C, gm, and Rds) they all have temperature variance (gm-C changes a lot with temperature, Op-amp with RC is the least theramally variant) C?
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aaron_do

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Re: channel select filter
Reply #5 - Aug 24^th, 2006, 5:14pm

It's gm-C...

so just OTA's and C's. I figured with a good bandgap reference i could keep the variation in the gm of the OTA to a minimum. I designed a simple bandgap and found that the total variation in the center frequency was about 15% from f0, mainly due to the slow-slow and fast-fast corners. So with the extra capacitor variation i expect 25% variation at worst. My Filter BW is 1 MHz around 2 MHz center, so i guess if I give a 2 MHz bandwidth i should be ok. The adjacent channel rejection is 0 dB (3 MHz) and the alternate channel rejection is 30 dB (8 MHz). What do you think?

thanks,
Aaron

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ACWWong

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Re: channel select filter
Reply #6 - Aug 25^th, 2006, 4:16am

aaron_do wrote on Aug 24^th, 2006, 5:14pm:

It's gm-C...

so just OTA's and C's. I figured with a good bandgap reference i could keep the variation in the gm of the OTA to a minimum. I designed a simple bandgap and found that the total variation in the center frequency was about 15% from f0, mainly due to the slow-slow and fast-fast corners. So with the extra capacitor variation i expect 25% variation at worst. My Filter BW is 1 MHz around 2 MHz center, so i guess if I give a 2 MHz bandwidth i should be ok. The adjacent channel rejection is 0 dB (3 MHz) and the alternate channel rejection is 30 dB (8 MHz). What do you think?

thanks,
Aaron

It depends on your system design. Can your ADC/Demodulator tolerate 0dB adjacent channel rejection ? Will it have addition digital filtering to take it out ?
What it the specification for the power in the adjacent channel to be handled? in some specs it can be bigger than the wanted channel, so in those systems i doubt your filter is good enough. If the system isn't tough, then thats great!
Anyway, looks like you've done well to get the gm variation down to 15% with on chip resistance. Maybe you might want to take a look at your process data to ensure the "corner" simulation is actually at an appropriate sigma (3 is good, and remember normal distribution variance is additive, so 2 indepedant equal weighed 3stddev figures is √18=4.2sigma).
As fc is proportional to gm/C to get 25% means you have C at about 8% variation.... also pretty good. In this case an external R would get you down in the realms of fc variation in the region of 10%.
Filter tuning can get to you guaranteed to 1~2%, but if thats not required, then your right not to create work for yourself.

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loose-electron

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Re: channel select filter
Reply #7 - Aug 25^th, 2006, 8:21am

Agree with prior post - and some additional comments

Your requirements are going to be set by what the system requires, and you should have "in hand" the min-max filter rejection requirements. Especally in an RF design, the "ducks in a row" on system performance requirements are important.

The variance mentioned sounds optimistic to me at first glance.

Have you done process-voltage-temperature corners?
Who's foundry modesl are you doing this with?
Have you mismatched PMOS/NMOS corners? (weak P, strong N and the opposite)
Have you determined min-max for caps?

those are some of the things I would take a look at.

As well, although not directly related to the filtering requirements, when it comes to system requirements, have you looked at linearity (IIP3) and noise needs (IRN)?

Jerry

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aaron_do

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Re: channel select filter
Reply #8 - Aug 25^th, 2006, 7:27pm

Hi guys,

thanks for the feedback. The PDK (CSM0.18) is based on silicon verified models which are supposed to be quite accurate at low frequency. I tested all corners (ff, ss, fs, sf) and a wide temperature variation. Bear in mind that i had a bandgap reference supplying an IPTAT to the filter. I got the capacitor variation from a data sheet...mim caps supposedly vary 10 % for the pdk.

I worked out the requirements of input referred noise and linearity and the IF blocks were ordered to relax requirements on the filter anyway since it seems to be the most power hungry. The filter attenuation requirements were based on ZigBee which is 0 dB adjacent channel rejection and 30 dB alternate channel rejection. With 5 MHz spacing and an IF of 2 MHz, the alternate and adjacent channels appear at 3 MHz and 8 MHz, so i figure i can set my corner frequency at 3 MHz since i don't need to reject the adjacent channel (am i right in assuming this? I based it on a paper i read).

The reason i've avoided on chip tuning so far is because i'm almost totally new to filter design. Is it difficult to implement/understand?

thanks,
Aaron

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loose-electron

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Re: channel select filter
Reply #9 - Aug 26^th, 2006, 2:06pm

OK, so this is an 802.15.4 receiverin the ISM band. Got it.

Tuning is not hard to do, so if you need it, then dont be scared of including it.

As for "silicon verified model" well there is a lot of bad models out there with issues. So question what you get for models. No matter who the foundry is. If you give me a foundry name I can let you know if they generally have model problems or not.

Jerry

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aaron_do

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Re: channel select filter
Reply #10 - Aug 27^th, 2006, 6:42pm

yep, its a research project.

Its Chartered Semiconductor in 0.18 um so its a mature process. The thing is they recently changed their process. I know for sure they changed their top metal thickness but all their device models seem to be different from the old PDK. Anyway thanks for all the help, I think i'll look into the on-chip tuning.

Aaron

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loose-electron

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Re: channel select filter
Reply #11 - Aug 28^th, 2006, 8:38am

OK, then this is the Chartered common foundry process, where the foundry process is similar between IBM, Chartered and a couple of others.

IBM generally gets their models right, Chartered has some problems.

Take a read through this as a sanity check on the models:

http://www.chipdesignmag.com/display.php?articleId=438&issueId=16

That's my "poke and prod" method to check out models.
I have designed on IBM's flavor of this, but not Chartered, so I am not sure which model set they are using.

Comment on "mature foundry models" - a lot of times, the models don't get updated past the point where the model team needs to move on to the next new CMOS node. At that point they get frozen and what you have is what you have. Usually withing a year after the technology is out getting used.

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aaron_do

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Re: channel select filter
Reply #12 - Aug 28^th, 2006, 8:57am

hmm...the 0.18 micron process has been available for a few years now and from what i understand lately our group has been having more and more first success (well...working but not always exactly right...its RF after all).

I read your article but i haven't had a chance to look around at the models, but from memory they seemed very detailed. They definately change with all corners and temperature simulations.

Aaron

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ACWWong

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Re: channel select filter
Reply #13 - Aug 28^th, 2006, 9:45am

As its a research project, and i guess you'll only be looking at acouple of samples of an MPW, there is no need to get so hung up on corners... Maybe i've been lucky but i have never had an MPW returned which was outside 2 sigma for polyR, cap, vth etc. on the process monitor data.

Nevertheless, nothing beats looking at measured data from the foundry, and judging yourself whether it is modelled correctly or not. Often the modelling is drastically pessimistic/optimistic, and openly wrong (ie the PDK shows how wrong they're modelling is !).
As to filter tuning, its quite straight forward, but will add design time for no benefit if your system has a robust ADC.

cheers
aw

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Re: channel select filter
Reply #14 - Aug 29^th, 2006, 9:34am

Process corner models tend to be pessimistic, as defined by the foundry. I consider it a CYA approach by model teams. In concept, the model variance sits inside a 1o inch diametr circle as measured on silicon, so they skew it out to a 14 inch diameter circle in the corner definitions to cover themselves.

Please feel free to substitute centimeters... :D

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