Geoffrey_Coram
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In one simulator (don't recall which), the implementation of the HiCUM transistor model was bad, and the terminal current reported was incorrect depending on whether the external base resistance Rbx was zero or not. Thus, it looked like KCL was violated.
For the node in question, you can: a) attach 0-V voltage sources between the node and each device terminal, then see which device disagrees with the V-src b) compute KCL for the device (ic + ib + ie + is = 0)
How bad is the mismatch, compared to the largest magnitude of the terminal currents?
How are you computing the current? Are you sure you are getting the right terminal currents? Eg, in a MOS, if you use id_chan for the drain current, you will be missing the diode current as well as the capacitive currents.
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