Jaylin,

  Could you provide more details about the driver design?
1) Is it all npn? Or npn-pnp?
2) Do you really expect the output to swing rail-to-rail, 0 to 18V?
3) How was the interconnect routed?
Also could you describe what you mean by burned out? Does the
interconnect fail? Do the base-emitter junctions short? These are
useful clues in understanding the source of the issue.

   There are a lot of bad things that can happen with bipolars.
a) Bipolars saturate and this limits the maximum swing range. In logic
   applications, Schottky diodes connected in reverse across the
   Base-Collector junction to prevent saturation. This limits the minimum
   output voltage to about Vbe-Vd,schottky. In general, it is hard to build
   an integrated high voltage Schottky and the package parasitics limit
   the usefulness of off-chip clamps for power designs.

b) When the bipolar saturates the parasitic, substrate pnp turns on
   and draws a lot of current. The buried N+ layer that forms the
   subcollector reduces collector series resistance and suppress
   substrate pnp beta reducing the likelyhood of latch-up.

c) There is some optimization involved in the placement of the isolation
   rings. If the isolation rings are placed to close, then the substrate-
   buried collector breaksdown and limits the output swing. If the
   isolation ring and substrate conatc are placed to far from the device
   then they don't short the substrate pnp B-E junction contributing to
   latch-up.

d) Routing interconnect is big challenge, the metal has to routed so the
   the interconnect resistance does not contribute to the voltage drop,
   does not fail due to electromigration. The interconnect to each emitter
   needs to be identical or the difference in Vbe will cause hot spots.
   Ideally, small resistors, "ballast resistors" are used to equalize the
   Vbe.

e) Bipolars are sensitive to secondary breakdown, you will need to ask
   the big brains to describe the physics. Basically, if the transistor is an
   18V transistor and the transistor can source and sink 2A does not
   mean the it can source and sink 2A at 18V. Usually it can handle a
   lot less.

f) Finally, you have not described the process junciton isolated or dielectrically
  isolated? Dielectrically isolated devices are more susceptable to device
  self-heating and thermal run-away.

g) What type of packaging are you using, are the dies thinned? How are the
   dies mounted in the package? Are you testing at full power at wafer test?

                                                                         Best Regards,

                                                                           Sheldon

Dear Sheldon & Jerry,

Thanks for your kindly suggestion.
There is more information:
1)It is all NPN struture.
2)the output swings from Vce_sat to VDD-2*Vbe-Vce_sat.
3)What does "interconnect routed" mean? Do you mean a reasonable metal connection in the layout?
 I didn't place the ballast resistor at the emitter of the big drive transistor for these small resistor
 will take great size in the layout,but I put very wide metal2 above the parallel transistors and pick
 up them one by one.
4)The testing is not wafer testing, the IC is tested on a socket after packaging.
5)The "burned out" I said means that in the testing, I give a 5V input to the IC, and VDD=6V at the first,
 it will output 4.6V, then I adjust the VDD up to 18V, a few "good IC" can output 16.6V, but Ivdd=34mA
 (the designed value should be smaller than 1mA, because the load of the IC is capacitor), under such
 large power consumption 34mA*18V, after 1 or 2 hours, the Ivdd jumps to several mA that is the
 current limit of the power supplier; but most of the IC is worse, when I increase the VDD up to 10V,
 the output voltage seems not to follow the VDD but oscillate about 8V, and the Ivdd become larger.
6)the process is juction isolated.
7)+/-2A current is the output peaking current, the during time is smaller than 100nS.
8)the design seems to be digital, but I have not put the schotty diode at the BC juction of transistor
 to avoid saturation, even for the big transistor at the output. Will it cause great problem?
9)the ground guard ring is not too close and too far from the device, the distance is the same as the
minimum distance between islands
10)the package is SOP and is said to sustain more than 600mW power consumption, and the die is some thin
  L/W=1.7


Thanks a lot &regards
Jay

Dear Jerry,

It is not convenient to show the schematic for it is a project, but I am very grateful for your and Sheldon's help.


Best Regards
Jay

The base emitter junction is going into a zener situation.

Due to that being a shallow junction area, thats not too surprising.

A lot of models in simulation do not include large signal effects of this nature.

Another example of a bad foundry model.