jaylin79
Junior Member
![* *](https://designers-guide.org/forum/Templates/Forum/default/starblue.gif)
Offline
Posts: 26
|
Dear Sheldon & Jerry,
Thanks for your kindly suggestion. There is more information: 1)It is all NPN struture. 2)the output swings from Vce_sat to VDD-2*Vbe-Vce_sat. 3)What does "interconnect routed" mean? Do you mean a reasonable metal connection in the layout? I didn't place the ballast resistor at the emitter of the big drive transistor for these small resistor will take great size in the layout,but I put very wide metal2 above the parallel transistors and pick up them one by one. 4)The testing is not wafer testing, the IC is tested on a socket after packaging. 5)The "burned out" I said means that in the testing, I give a 5V input to the IC, and VDD=6V at the first, it will output 4.6V, then I adjust the VDD up to 18V, a few "good IC" can output 16.6V, but Ivdd=34mA (the designed value should be smaller than 1mA, because the load of the IC is capacitor), under such large power consumption 34mA*18V, after 1 or 2 hours, the Ivdd jumps to several mA that is the current limit of the power supplier; but most of the IC is worse, when I increase the VDD up to 10V, the output voltage seems not to follow the VDD but oscillate about 8V, and the Ivdd become larger. 6)the process is juction isolated. 7)+/-2A current is the output peaking current, the during time is smaller than 100nS. 8)the design seems to be digital, but I have not put the schotty diode at the BC juction of transistor to avoid saturation, even for the big transistor at the output. Will it cause great problem? 9)the ground guard ring is not too close and too far from the device, the distance is the same as the minimum distance between islands 10)the package is SOP and is said to sustain more than 600mW power consumption, and the die is some thin L/W=1.7
Thanks a lot ®ards Jay
|