We are designing a VCO by using CMOS ring osc, trying to achieve minimum 3GHz for all the corners. The target process is S  M I C 0.13um generic or S M I C 0.13um LV.
The VCO circuit itself, is a simple diff buffer than has both MOS and current source load.
When running at 0.13um LV process, the result is very good, the VCO can easily reach 3.3G even with full RC extraction. However, when we simulate the same circuit at 0.13um generic (1.2V), the result is really bad, it can hardly achieve 2.2GHz at post-layout stage. We tried to increase the tail current and also reduce output impedance of VCO circuit, it will improve a little, but still not as good the LV one.

I'm wondering if it is a process limitation that we can not reach 3.3G, or is there any other thing we can do to improve the VCO circuit's bandwidth?

really appreciate for any help.

thanks for the reply, I'm not 100% sure if I got the idea correctly. Do you mean "Use multiple phases out of the ring oscillator?".  20 delay stages sounds quite a lot, which remind me about DLL design.

My current design is targeted on high speed but very low jitter, for time being there are only four delay cells in VCO and I took the output from one only.   To me, more delay stage means more jiter due to varation of each delay cell, so the multiple  phase solution might not work here.

The thing is, does 0.13um generic process has limited a single stage diff amp bandwidth to be less than 3G? Or it is just because I didn't do the circuit right?  

thanks and regards