Hi all,
I would like to perform mixed/mode simulations (using AMS-Designer through the Hirachy-Editor->AMS-Plugin environment) including post-layout SDF delays for verilog digital modules.
From the AMS Environment User Guide, I read that it is necessary to fill the field "AMS-Plugin->AMS Options->Elaborator->SDF annotation -> Use SDF command file" but it seems to me it is not enough since the SDF delays are not considered and all the digital gates keep their original indicative delay time (e.g. 1ns as default).
I filled the field above either with the absolute path to the SDF delay file or with a file containing only the following verilog expression:
initial $sdf_annotate("sdf_delayfile.sdf", name_top_module)
I am not sure if this file can be considered a "SDF command file" but I tried anyway
In both cases the sdf delays are ignored!
I also reduced the default timescale for verilog modules in order to avoid any "delay rounding" but still it does not work.
Does anybody of you experimented such behaviour? Do you have any idea?
Thanks in advance and bye!
Cri