In power down(shutdown) mode,

I want to see if the circuit has no floating nodes which might cause leakage current.

How can I do this simulation in spectre?

Just apply power down signal and watch the current out of the power supply?

If the current goes down near to zero, is it safe for leakage current?
and does it also mean there is no floating nodes?

In my opinion, even if there is no leakage current, there could be a floating node of which potential is zero.

I think this node may have leakage problem in a real circuit. Am I correct?

Thanks in advance.

Power cycling, -- having been severely bit by this one ---

Suggest - simulating of power cycles often does not account for all the parasitic capacitances in the system, and a floating gate of a transistor is unpredictable in what it is going to do.

Suggest - If you are in PD mode, every single NMOS current source gate should be yanked to ground, and every single PMOS current source gate should be yanked to power rail. Also any and all current paths need to be defined as solidly switched off, using some form of a switch. No opening the circuit and letting it float down to ground as it discharges.

Been there, done that, gotten bitten, had to respin the chip.

loose-electron wrote on Aug 29^th, 2006, 9:43am:


What does "respin the chip" mean?  ::)

Is there any rule of thub to determine the size of the switch which yanks the gate to ground or power rail?

One more thing sometimes using minimum length can cause large leakage at some corners particularly if you are using core devices. So if at some corner the leakage is large try longer length device. I guess this is more pronounced for 0.18um and below.